Broadband LNA with filter

1. A low noise amplifier (LNA), comprising:

an LNA input that receives a signal from an antenna;

a first internal amplifier having an input that is coupled to the LNA input;

an internal filter having an input coupled to the output of the first internal amplifier;

a second internal amplifier having an input that is coupled to the output of the internal filter; and

a feedback element having an input that is coupled to the output of the second internal amplifier and an output that is coupled to the input of the first internal amplifier, wherein:

the internal filter is configured to pass signals within a frequency range through to the output of the internal filter.

2. The system of claim 1 , wherein the width of the frequency range is adjustable.

3. The system of claim 1 , wherein the center of the frequency range is adjustable.

4. The system of claim 1 , wherein the feedback element from the output of the second internal amplifier to the input of the first internal amplifier includes a resistor.

5. The system of claim 1 further comprising a resistor having a first end that is coupled to the input of the second internal amplifier and a second end that is coupled to the output of the second internal amplifier.

6. The system of claim 5 , wherein the second internal amplifier is an inverting amplifier.

7. The system of claim 1 , wherein the first internal amplifier is an inverting amplifier.

8. The system of claim 1 , wherein the internal filter includes a low pass filter.

9. The system of claim 1 , wherein the internal filter includes a band pass filter.

10. The system of claim 1 , wherein the internal filter includes:

a first frequency shifter that receives the input of the internal filter and outputs a signal shifted up in frequency;

a band pass filter that receives the signal shifted up in frequency and outputs a filtered signal; and

a second frequency shifter that receives the filtered signal and outputs a signal shifted down in frequency.

11. The system of claim 10 , wherein the first and the second frequency shifters are configured to shift up and shift down in frequency by the same amount.

12. The system of claim 10 , further comprising:

a first variable oscillator, wherein the frequency of the first variable oscillator controls the amount the first frequency shifter shifts up in frequency; and

a second variable oscillator, wherein the frequency of the second variable oscillator controls the amount the second frequency shifter shifts down in frequency.

13. The system of claim 1 , wherein the internal filter includes a negative resistor.

14. The system of claim 1 , wherein the internal filter includes a multi-stage filter.

15. The system of claim 14 , wherein the multi-stage filter includes:

a common gate transistor having a source and a drain; and

a capacitor, where a first end of the capacitor is coupled to the output of a first stage of the multi-stage filter, a second end of the capacitor is coupled to the source of the common gate transistor, and the drain of the common gate transistor is coupled to the input of a second stage of the multi-stage filter.

16. The system of claim 14 , wherein the first stage and/or the second stage include(s) a negative resistor.

17. The system of claim 14 , wherein the first stage and the second stage are identical.

18. The system of claim 14 , wherein the multi-stage filter further includes:

a second common gate transistor; and

a third common gate transistor, where the drain of the second common gate transistor is coupled to the input of the first stage and the source of the third common gate transistor is coupled to the output of the second stage.

19. The system of claim 18 , wherein the second common gate transistor and/or the third common gate transistor is/are used in a mixer.

20. A negative resistor, comprising:

a first n-type transistor with a load facing terminal and a shared terminal;

a second n-type transistor with a load facing terminal and a shared terminal;

a first p-type transistor with a load facing terminal and a shared terminal;

a second p-type transistor with a load facing terminal and a shared terminal;

a filter; and

a first, second, third, fourth and fifth capacitor, wherein:

the shared terminal of the first n-type transistor is connected to the shared terminal of the first p-type transistor;

the shared terminal of the second n-type transistor is connected to the shared terminal of the second p-type transistor;

a first end of the first capacitor is coupled to the load facing terminal of the first n-type transistor and a second end of the first capacitor is coupled to the shared terminal of the first n-type transistor;

a first end of the second capacitor is coupled to the load facing terminal of the second n-type transistor and a second end of the second capacitor is coupled to the shared terminal of the second n-type transistor;

a first end of the third capacitor is coupled to the load facing terminal of the first p-type transistor and the second end of the third capacitor is coupled to the shared terminal of the first p-type transistor;

a first end of the fourth capacitor is coupled to the load facing terminal of the second p-type transistor and the second end of the fourth capacitor is coupled to the shared terminal of the second p-type transistor;

a first end of the fifth capacitor is coupled to the shared terminal of the first n-type transistor and the second end of the fifth capacitor is coupled to the shared terminal of the second n-type transistor;

the load facing terminal of the first n-type transistor is coupled to the filter;

the load facing terminal of the second n-type transistor is coupled to the filter;

the load facing terminal of the first p-type transistor is coupled to the filter; and

the load facing terminal of the second p-type transistor is coupled to the filter.

21. The system of claim 20 , wherein the negative resistor further includes a first, second, third and fourth inductor, wherein:

the first end of the first inductor is coupled to the load facing terminal of the first n-type transistor and the second end of the first inductor is coupled to a supply or other low impedance node;

the first end of the second inductor is coupled to the load facing terminal of the second n-type transistor and the second end of the second inductor is coupled to a supply or other low impedance node;

the first end of the third inductor is coupled to the load facing terminal of the first p-type transistor and the second end of the third inductor is coupled to a ground or other low impedance node; and

the first end of the fourth inductor is coupled to the load facing terminal of the second p-type transistor and the second end of the fourth inductor is coupled to a ground or other low impedance node.

22. The system of claim 21 , wherein the first and second inductors include coupled transformers including a first loop and a second loop.

23. The system of claim 22 , wherein the magnetic (B) field of the first loop substantially cancels the magnetic (B) field of the second loop.

24. A method, comprising:

receiving a signal from an antenna via an LNA input;

amplifying the received signal using a first internal amplifier having an input that is coupled to the LNA input;

filtering the amplified signal using an internal filter having an input coupled to the output of the first internal amplifier;

amplifying the output signal from the internal filter using a second internal amplifier having an input coupled to the output of the internal filter; and

feeding back the output signal of the second amplifier to the input of the first amplifier using a feedback element having an input that is coupled to the output of the second amplifier and an output that is coupled to the input of the first internal amplifier, wherein:

the internal filter is configured to pass signals within a frequency range through to the output of the internal filter.