Liquid crystal display and inversion drive method

1 . An apparatus comprising:

a first output buffer block including a first buffer to control a first output voltage to a first data line in a liquid crystal display (LCD) and a second buffer to control a second output voltage to a second data line in the LCD;

a second output buffer block including a third buffer to control a third output voltage to a third data line in the LCD and a fourth buffer to control a fourth output voltage to a fourth data line in the LCD; and

a first polarity signal line to invert a polarity of the first output voltage at a first time point and a second polarity signal line to invert a polarity of the third output voltage at a second time point not coinciding with the first time point.

2 . The apparatus of claim 1 , wherein the first buffer includes p-type transistors to drive the polarity of the first output voltage to a positive polarity when the first polarity signal line conducts a positive signal.

3 . The apparatus of claim 2 , wherein the second buffer includes n-type transistors to drive a polarity of the second output voltage to a negative polarity when the first polarity signal line conducts a positive signal.

4 . The apparatus of claim 1 , wherein the first output voltage is positive and the second output voltage is negative when the first polarity signal line conducts a positive signal, and the first output voltage is negative and the second output voltage is positive when the first polarity signal line conducts a negative signal.

5 . The apparatus of claim 4 , wherein the third output voltage is positive and the fourth output voltage is negative when the second polarity signal line conducts a positive signal, and the third output voltage is negative and the fourth output voltage is positive when the second polarity signal line conducts a negative signal.

6 . The apparatus of claim 1 , wherein the first time point is to be separated from the second time point by less than a time period required to refresh the first data line.

7 . The apparatus of claim 1 , wherein the first polarity signal line is to invert a polarity of the second output voltage at the first time point and the second polarity signal line is to invert a polarity of the fourth output voltage at the second time point.

8 . The apparatus of claim 1 , further comprising:

a third output buffer block including a fifth buffer to control a fifth output voltage to a fifth data line in the LCD and a sixth buffer to control a sixth output voltage to a sixth data line in the LCD;

a fourth output buffer block including a seventh buffer to control a seventh output voltage to a seventh data line in the LCD and an eighth buffer to control an eighth output voltage to an eighth data line in the LCD; and

the first polarity signal line to invert a polarity of the fifth output voltage at the first time point and the second polarity signal line to invert a polarity of the seventh output voltage at the second time point.

9 . A method comprising:

using a first polarity signal line, coupled to a first output buffer block that includes a first buffer, to invert a first output voltage to a first data line in a liquid crystal display (LCD) at a first time point; and

using a second polarity signal line, coupled to a second output buffer block that includes a second buffer, to invert a second output voltage to a second data line in the LCD at a second time point not coinciding with the first time point.

10 . The method of claim 9 , comprising:

using the first polarity signal line, coupled to the first output buffer block that includes a third buffer, to invert a third output voltage to a third data line in the LCD at the first time point; and

using the second polarity signal line, coupled to the second output buffer block that includes a fourth buffer, to invert a fourth output voltage to a fourth data line in the LCD at the second time point.

11 . The method of claim 10 , comprising:

using the first polarity signal line, coupled to a third output buffer block that includes a fifth buffer, to invert a fifth output voltage to a fifth data line in the LCD at the first time point; and

using the second polarity signal line, coupled to a fourth output buffer block that includes a sixth buffer, to invert a sixth output voltage to a sixth data line in the LCD at the second time point.

12 . The method of claim 9 , comprising:

using the first polarity signal line to invert the first output voltage to a first polarity at the first time point; and

using the second polarity signal line to invert the second output voltage to a second polarity at the second time point.

13 . The method of claim 12 , comprising:

conducting a signal of the first polarity on the first polarity signal line to invert the first output voltage to the first polarity at the first time point; and

conducting a signal of the second polarity on the second polarity signal line to invert the second output voltage to a second polarity at the second time point.

14 . The method of claim 9 , comprising:

using the first polarity signal line to invert the first output voltage to a first polarity at the first time point; and

using the second polarity signal line to invert the second output voltage to the first polarity at the second time point.

15 . The method of claim 9 , further comprising inverting the second output voltage at the second time point which follows the first time point by less than a time period required to refresh the first data line.

16 . An liquid crystal display (LCD) comprising:

a first output buffer block group and a second output buffer block group to control voltage polarity of signals transmitted via data lines included in a liquid crystal display (LCD) panel; and

two polarity signal lines to respectively control the first and second output buffer block groups such that at least one voltage polarity of a signal transmitted via a data line controlled by the first output buffer block group inverts non-simultaneously with at least one voltage polarity of a signal transmitted via a data line controlled by the second output buffer block group.

17 . The LCD of claim 16 , wherein each of the output buffer block groups includes a first buffer block that further includes a first buffer to control a voltage polarity of a signal transmitted via a first output terminal and a second buffer to control a voltage polarity of a signal transmitted via a second output terminal.

18 . The LCD of claim 17 , wherein the first buffer includes p-type transistors to drive the signal transmitted via the first output terminal to a positive polarity.

19 . The LCD of claim 17 , wherein the second buffer includes n-type transistors to drive the signal transmitted via the second output terminal to a negative polarity.

20 . The LCD of claim 16 , wherein the time difference for polarity inversion of the two polarity signal lines is, 1/n T, where T is a time period required to refresh the first data line and n is greater than 1.