Wiring structure, array substrate, display device having the same and method of manufacturing the same
A wiring structure includes a substrate, a copper oxide layer having 16˜39 at % oxygen on the substrate and a copper layer on the copper oxide layer. The copper oxide layer has a thickness of 10-1000 Å and the copper layer has a thickness of 300-8000 Å. The copper layer and the copper oxide layer further have an alloy element less than 10 wt % and the alloy element is selected from the group of Ag, Ni, Mg, Zr, N.
1 . A wiring structure comprising;
a substrate;
a copper oxide layer having 16˜39 at % oxygen on the substrate; and
a copper layer on the copper oxide layer.
2 . The wiring structure of claim 1 , wherein the copper oxide layer has a thickness of 10-1000 Å.
3 . The wiring structure of claim 2 , wherein the copper layer has a thickness of 300-20000 Å.
4 . The wiring structure of claim 3 , wherein the copper layer and the copper oxide layer further comprise a alloy element less than 10 wt %.
5 . The wiring structure of claim 4 , wherein the alloy element selects from the group of Ag, Ni, Mg, Zr, N.
6 . The wiring structure of claim 2 , wherein the copper layer and the copper oxide layer further comprise an alloy element less than 10 wt %.
7 . The wiring structure of claim 6 , wherein the alloy element selects from the group of Ag, Ni, Mg, Zr, N.
8 . The wiring structure of claim 1 , wherein the copper layer has a thickness of 300-20000 Å.
9 . The wiring structure of claim 8 , wherein the copper layer and the copper oxide layer further comprise a alloy element less than 10 wt %.
10 . The wiring structure of claim 9 , wherein the alloy element selects from the group of Ag, Ni, Mg, Zr, N.
11 . The wiring structure of claim 1 , wherein the copper layer and the copper oxide layer further comprise a alloy element less than 10 wt %.
12 . The wiring structure of claim 11 , wherein the alloy element selects from the group of Ag, Ni, Mg, Zr, N.
13 . A thin film transistor, comprising:
a gate electrode comprising a copper layer and copper oxide layer on an insulating substrate;
a semiconductor layer on the gate electrode;
a source and drain electrode on the semiconductor layer
14 . The thin film transistor of claim 13 , the copper oxide layer having an 16 at %˜39 at % oxygen.
15 . The thin film transistor of claim 14 , the thickness of the copper oxide layer is 10-1000 Å.
16 . The thin film transistor of claim 15 , wherein the copper layer has a thickness of 300-20000 Å.
17 . The thin film transistor of claim 16 , wherein the copper layer and the copper oxide layer further comprise an alloy element less than 10 wt %.
18 . The wiring structure of claim 17 , wherein the alloy element selects from the group of Ag, Ni, Mg, Zr, N.
19 . The thin film transistor of claim 13 , the thickness of the copper oxide layer is 10-1000 Å.
20 . The thin film transistor of claim 13 , wherein the copper layer has a thickness of 300-20000 Å.
21 . The thin film transistor of claim 13 , wherein the copper layer and the copper oxide layer further comprise an alloy element less than 10 wt %.
22 . The wiring structure of claim 21 , wherein the alloy element selects from the group of Ag, Ni, Mg, Zr, N.
23 . A method of forming a wiring structure comprising;
forming a copper oxide layer having 16˜39 at % oxygen on a substrate; and
forming a copper layer on the copper oxide layer.
24 . A method forming a thin film transistor comprising;
forming a gate electrode with copper layer and copper oxide layer;
forming a semiconductor layer on the gate electrode;
forming a source and drain electrode on the semiconductor layer.