Semiconductor nonvolatile memory device
View Patent ↗An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
1. An integrated semiconductor nonvolatile memory, comprising:
a first insulated-gate field effect transistor with a first gate having a gate electrode formed in a stacked fashion on a semiconductor substrate via an insulating film;
a second insulated-gate field effect transistor with a second gate including a charge storage film formed in a region on said semiconductor substrate adjacent to said first insulated-gate field effect transistor;
a first channel formed in said semiconductor substrate, below said first insulated-gate field effect transistor;
a second channel formed in said semiconductor substrate, below said second insulated-gate field effect transistor and adjacent to said first channel so as to be electrically connected thereto; and
a first diffusion-layer electrode and second diffusion-layer electrode formed at one end of said first channel and an opposite end of said second channel, respectively, so as to sandwich a region on said semiconductor substrate where said first channel and said second channel are formed;
wherein programming is executed by applying a voltage to said second gate and injecting electrons and a hole from a region of said second channel into said charge storage film; and
wherein the programming is executed by conducting multi-step voltage application to said second gate, and each of voltages applied in a multi-step manner is determined in accordance with a predetermined reference table.
2. The integrated semiconductor nonvolatile memory according to claim 1 , wherein the reference table is stored in accordance with circuit element composition.
3. The integrated semiconductor nonvolatile memory according to claim 1 , wherein the multi-step voltage application is followed by verification.
4. An integrated semiconductor nonvolatile memory, comprising:
a first insulated-gate field effect transistor with a first gate having a gate electrode formed in a stacked fashion on a semiconductor substrate via an insulating film;
a second insulated-gate field effect transistor with a second gate including a charge storage film formed in a region on said semiconductor substrate adjacent to said first insulated-gate field effect transistor;
a first channel formed in said semiconductor substrate, below said first insulated-gate field effect transistor;
a second channel formed in said semiconductor substrate, below said second insulated-gate field effect transistor and adjacent to said first channel so as to be electrically connected thereto; and
a first diffusion-layer electrode and second diffusion-layer electrode formed at one end of said first channel and an opposite end of said second channel, respectively, so as to sandwich a region on said semiconductor substrate where said first channel and said second first channel are formed;
wherein programming and erasure are executed by applying voltage to said second gate and injecting electrons and a hole from a region of said second channel into said charge storage film; and
wherein the programming and erasure are executed by conducting multi-step voltage application to said second gate a plurality of times, and each of multi-step voltages applied is determined in accordance with a predetermined reference table.
5. The integrated semiconductor nonvolatile memory according to claim 4 , wherein the reference table is stored in accordance with circuit element composition.
6. The integrated semiconductor nonvolatile memory according to claim 4 , wherein the multi-step voltage application is followed by verification.