Circuit arrangement and method for power regulation and amplifier arrangement

1. A circuit arrangement comprising:

a signal input to feed in a level value;

a signal output to output a control value;

a control input to feed in a power control word; and

a compensation device coupled to the signal input, the signal output and the control input, the compensation device configured to derive the control value from the level value depending on the power control word;

wherein the deriving comprises determining a deviation of the level value from a desired value, which is dependent on the power control word, and multiplication of the deviation of the level value by a compensation factor, which is dependent on the power control word.

2. The circuit arrangement of claim 1 , wherein the compensation device comprises an integration filter and is configured to derive the control value via the integration filter.

3. The circuit arrangement of claim 1 , wherein the compensation device is coupled to the signal input via an analogue-to-digital converter, and wherein the analogue-to-digital converter is configured to determine a digital level value and is configured to derive the control value from the digital level value via digital signal processing.

4. The circuit arrangement of claim 3 , wherein the compensation device is coupled to the signal output via a digital-to-analogue converter configured to derive the control value from a digitally derived control value.

5. The circuit arrangement of claim 1 , wherein the compensation device comprises a compensation filter and the compensation device is configured to derive the control value via the compensation filter and to determine filter coefficients of the compensation filter depending on the power control word.

6. The circuit arrangement of claim 5 , wherein the compensation device comprises a memory device configured to store and retrieve at least one of respective desired values, respective compensation factors, and respective filter coefficients, depending on a respective power control word.

7. The circuit arrangement of claim 6 , wherein the compensation device is configured to determine at least one of compensation factors and filter coefficients of the compensation filter by interpolation of values stored in the memory device.

8. The circuit arrangement of claim 1 , further comprising a correction device, the correction device configured to determine a correction factor depending on the level value and the control value and to derive the control value by multiplication by the correction factor.

9. The circuit arrangement of claim 8 , wherein the correction device is configured to determine a differential gain factor from the level value and the control value and to derive the correction factor from the differential gain factor when determining the correction factor.

10. The circuit arrangement of claim 9 , wherein the correction device is configured to determine the differential gain factor by division of the deviation of the level value and a deviation of the control value.

11. The circuit arrangement of claim 9 , wherein the correction device is configured to derive the correction factor from the differential gain factor by multiplication by a scaling factor.

12. The circuit arrangement of claim 1 , wherein the signal input is coupled to a detector output of a detection device coupled to an amplifier, the detector output to output a level value of the amplifier, and wherein the signal output is coupled to a setting input of the amplifier.

13. The circuit arrangement of claim 1 , wherein the circuit arrangement is included in a mobile communications device.

14. A circuit arrangement comprising:

a signal input to feed in a level value;

a signal output to output a control value;

a control input to feed in a power control word; and

a compensation device including:

a first parameter unit to derive a desired value depending on the power control word;

a second parameter unit to derive a compensation factor in depending on the power control word;

a difference unit, and

a series circuit formed by a multiplication unit and an integration filter, the series circuit coupled, on an output side, to the signal output, and an input of the

multiplication unit is coupled to the second parameter unit;

wherein the difference unit comprises a first input coupled to the first parameter unit, a second input coupled to the signal input, and an output coupled to the series circuit.

15. The circuit arrangement of claim 14 , wherein the series circuit comprises a compensation filter and the compensation device comprises a third parameter unit to derive filter coefficients of the compensation filter depending on the power control word.

16. The circuit arrangement of claim 14 , wherein the difference unit is coupled to the signal input via an analogue-to-digital converter, the series circuit is coupled to the signal output via a digital-to-analogue converter, or a combination thereof.

17. The circuit arrangement of claim 14 , further comprising a correction device to determine a correction factor, wherein the correction device is coupled, on an input side, to the signal input and the signal output and, on an output side, to the multiplication unit.

18. The circuit arrangement of claim 17 , wherein the correction device is configured to determine a differential gain factor by division of a deviation of the level value and a deviation of the control value and to derive the correction factor from the differential gain factor by multiplication by a scaling factor.

19. The circuit arrangement of claim 14 , wherein the signal input is coupled to a detector output of a detection device coupled to an amplifier, the detector output to output a level value of the amplifier, and wherein the signal output is coupled to a setting input of the amplifier.

20. A method comprising:

feeding in a level value from an amplifier;

determining a desired value depending on a power control word;

determining a deviation of the level value from the desired value;

determining a compensation factor depending on the power control word;

deriving a control value depending on the deviation of the level value from the desired value, wherein deriving the control value comprises a multiplication by the compensation factor; and

outputting the control value to the amplifier.

21. The method of claim 20 , wherein deriving the control value comprises an integrated filtering.

22. The method of claim 20 , wherein feeding in the level value comprises an analogue-to-digital conversion.

23. The method of claim 20 , wherein outputting the control value comprises a digital-to-analogue conversion.

24. The method of claim 20 , wherein filter coefficients are determined depending on the power control word, and wherein deriving the control value is via a compensation filter function with the filter coefficients.

25. The method of claim 24 , further comprising determining at least one of the desired value, the compensation factor, and the filter coefficients depending on the power control word.

26. The method of claim 25 , wherein determining at least one of the compensation factor and the filter coefficients comprises an interpolation of stored values.

27. The method of claim 20 , wherein a correction factor is determined depending on the level value and the control value, and wherein deriving the control value comprises a multiplication by the correction factor.

28. The method of claim 27 , wherein determining the correction factor comprises deriving a differential gain factor from the level value and the control value and deriving the correction factor from the differential gain factor.

29. The method of claim 28 , wherein deriving the differential gain factor is effected by division of the deviation of the level value and a deviation of the control value.

30. The method of claim 29 , wherein the division when deriving the differential gain factor comprises a shift operation.

31. The method of claim 28 , wherein the correction factor is derived from the differential gain factor by multiplication by a scaling factor.