IP Library Granted Patent US 7,956,422
Granted Patent B2
US 7,956,422 · App. 12/234,515 · Granted Jun 7, 2011

Semiconductor device, method for fabricating the same, and transformer circuit using the same

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Quick Facts
Patent No.
US 7,956,422
App. No.
12/234,515
Granted
Jun 7, 2011
Kind
B2
Abstract

A semiconductor device, a method for fabricating the same, and a transformer circuit using the same are disclosed. The semiconductor device includes a trench metal oxide semiconductor (MOS) transistor for switching a load of current supplied from a power source, and a boost controller for controlling driving of the trench MOS transistor, the boost controller being formed with the trench MOS transistor on a single semiconductor device to form an integrated structure. In this structure, the physical space of the semiconductor device is reduced, thereby reducing the size of a DC-DC transformer circuit using the semiconductor device. It is possible to obtain finely-adjusted output values by controlling values of the ripple current and ripple voltage. A desired operational stability according to a variation in temperature can also be secured.

Claims (66)

1. A semiconductor device comprising:

a trench metal oxide semiconductor (MOS) transistor adapted to provide a current load from a power source; and

a boost controller adapted or configured to control the trench MOS transistor, the boost controller being a single semiconductor device with the trench MOS transistor to form an integrated structure, wherein the boost controller comprises:

a lightly-doped P type epitaxial layer on the semiconductor substrate;

an N type well and a first P type well having a predetermined depth in the P type epitaxial layer;

an oxide film on each of the N type well and the P type well;

P and N type polysilicon gates on the oxide film, respectively;

P type source and drain electrodes in regions at opposite sides of the gate in the N type well;

N type source and drain electrodes in regions at opposite sides of the gate in the P type well;

a common drain on a back surface of the heavily-doped N+ type semiconductor substrate; and

a device isolation layer adapted or configured to isolate the boost controller from the trench MOS transistor.

2. The semiconductor device according to claim 1 , wherein the trench MOS transistor comprises:

a heavily-doped N+ type semiconductor substrate;

a lightly-doped N type layer on or in the heavily-doped N+ type semiconductor substrate;

a second P type well having a predetermined depth in the lightly-doped N type layer;

a gate in a trench in the lightly-doped N type layer extending through the second P type well;

N type sources adjacent to the gate;

a contact layer in contact with the N type sources;

an insulating layer covering the gate; and

the common drain on the back surface of the heavily-doped N+ type semiconductor substrate.

3. The semiconductor device according to claim 2 , wherein the trench MOS transistor further comprises:

a silicon oxide film between the gate and an inner wall of the trench.

4. The semiconductor device according to claim 3 , wherein the silicon oxide film has a thickness of 50 to 500 Å.

5. The semiconductor device according to claim 2 , wherein the trench has a depth of 1 to 2 μm.

6. The semiconductor device according to claim 2 , wherein the trench MOS transistor comprises:

a plurality of gates in a corresponding plurality of trenches.

7. The semiconductor device according to claim 1 , wherein the lightly-doped P type epitaxial layer has a thickness of 2.5 to 10 μm.

8. The semiconductor device according to claim 1 , wherein the trench MOS transistor concentrically surrounds the boost controller.

9. The semiconductor device according to claim 1 , wherein the common drain on the back surface of the heavily-doped N+ type semiconductor substrate comprises silver, copper or aluminum.

10. A transformer circuit, comprising:

a power source supplying a power;

an inductor adapted or configured to accumulate and discharge current;

a capacitor adapted or configured to charge, store and discharge energy from the inductor;

a diode adapted or configured to prevent a flow of current from the capacitor to the inductor; and

a semiconductor device adapted or configured to control a current load from the power source, energy accumulation, or discharge of the inductor, wherein the semiconductor device comprises:

a trench metal oxide semiconductor (MOS) transistor adapted or configured to switch the current load from the power source; and

a boost controller adapted or configured to control turning the trench MOS transistor on and off, the boost controller being a single semiconductor device with the trench MOS transistor to form an integrated structure, wherein the boost controller comprises:

a lightly-doped P type epitaxial layer on the semiconductor substrate;

an N type well and a P type well having a predetermined depth in the P type epitaxial layer;

an oxide film on each of the N type well and the P type well;

P and N type polysilicon gates on the oxide film, respectively;

P type source and drain electrodes in regions at opposite sides of the gate in the N type well;

N type source and drain electrodes in regions at opposite sides of the gate in the P type well;

a common drain on a back surface of the heavily-doped N+ type semiconductor substrate; and

a device isolation layer adapted or configured to isolate the boost controller from the trench MOS transistor.

11. The transformer circuit according to claim 10 , wherein the transformer circuit controls the current load from the power source, through the semiconductor device, to output a voltage equal to or higher than a voltage from the power source.

12. The transformer circuit according to claim 10 , further comprising:

a temperature sensor adapted or configured to detect a temperature or amount of heat from the semiconductor device, and thereby control an operation of the semiconductor device.

13. The transformer circuit according to claim 10 , wherein the inductor is coupled to the power source.

14. The transformer circuit according to claim 10 , wherein the lightly-doped P type epitaxial layer has a thickness of 2.5 to 10 μm.

15. The transformer circuit according to claim 10 , wherein the common drain on the back surface of the heavily-doped N+ type semiconductor substrate comprises silver, copper or aluminum.

16. The transformer circuit according to claim 10 , wherein the trench MOS transistor comprises:

a heavily-doped N+ type semiconductor substrate;

a lightly-doped N type layer on or in the heavily-doped N+ type semiconductor substrate;

a P type well having a predetermined depth in the lightly-doped N type layer;

a gate in a trench in the lightly-doped N type layer extending through the P type well;

N type sources adjacent to the gate;

a contact layer in contact with the sources;

an insulating layer covering the gates; and

the common drain on the back surface of the heavily-doped N+ type semiconductor substrate.

17. The transformer circuit according to claim 16 , wherein the trench MOS transistor further comprises:

a silicon oxide film between the gate and an inner wall of the trench, wherein the silicon oxide film has a thickness of 50 to 500 Å.

18. The transformer circuit according to claim 16 , wherein the trench MOS transistor comprises:

a plurality of gates in a corresponding plurality of trenches.

19. The transformer circuit according to claim 18 , wherein the trench MOS transistor concentrically surrounds the boost controller.

20. The transformer circuit according to claim 18 , wherein each of the trenches has a depth of 1 to 2 μm.

Assignments (2)
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD.
Reel/Frame 044559/0819 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2008
From: JANG, BYUNG TAK
To: DONGBU HITEK CO., LTD.
Reel/Frame 021566/0854 →