IP Library Granted Patent US 8,136,080
Granted Patent B2
US 8,136,080 · App. 12/234,817 · Granted Mar 13, 2012

Graphic rendering of circuit positions

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Quick Facts
Patent No.
US 8,136,080
App. No.
12/234,817
Granted
Mar 13, 2012
Kind
B2
Abstract

A method may include receiving circuit information from a backend circuit test system and grouping components in the circuit information into collections by types, the types including segments, equipment, ports, and connections. The method may further include positioning, based on the grouping by types, the components from the circuit information for presentation of a circuit design on a display, and performing path rendering for the circuit design based on the positioning of the components. The method may also include sending an output file with the path rendering to a web browser.

Claims (75)

1. A method, comprising:

receiving, by at least one device, circuit information from a backend circuit test system;

grouping, by the at least one device, components in the circuit information into collections by types, said grouping comprising identifying each component as one of a segment, equipment, a port, or a connection;

positioning, by the at least one device and based on the grouping by types, the components from the circuit information for presentation of a circuit design on a display, where

positioning the components comprises positioning each port on one of each piece of equipment, and

positioning each port on one of each piece of equipment comprises defining a best edge of each piece of equipment, where the best edge includes an edge that minimizes overlap of a connection with other components;

performing, by the at least one device, path rendering for the circuit design based on the positioning of the components; and

sending, by the at least one device, an output file with the path rendering to a web browser.

2. The method of claim 1 , where positioning the components comprises:

following interconnectivity of the components in sequence to identify one or more segments,

assigning each segment to a logical column,

positioning each segment within the logical column, and

positioning each piece of equipment within one or more segments.

3. The method of claim 2 , where assigning each segment to a logical column comprises traversing each segment using a width-first n-array tree traversal based on the connectivity associated with each of the segments.

4. The method of claim 2 , where a number of segments in the logical column is optimized according to a rule set that advances a segment from an assigned default column to a preceding column.

5. The method of claim 2 , where both a clockwise orientation and a counterclockwise orientation of SONET rings are used to prevent connections from crossing.

6. The method of claim 2 , where positioning each piece of equipment within one or more segments comprises:

adding non-visible elements to force distribution of equipment around the one or more segments.

7. The method of claim 1 , where each segment comprises one of a linear segment or a synchronous optical networking (SONET) ring.

8. The method of claim 1 , where performing path rendering for the circuit design based on the positioning of the components comprises:

sorting the components by type;

appending header information to an output code file;

rendering the connectors to the output code file;

after rendering the connectors, rendering the equipment to the output code file;

after rendering the equipment, rendering the ports to the output code file;

after rendering the ports, rendering labels to the output code file; and

appending footer information to the output code file.

9. The method of claim 8 , where the header information comprises:

a definition of a scalable vector graphics (SVG) object used to represent a component.

10. A device, comprising:

means for receiving circuit information from a backend circuit test system;

means for grouping components in the circuit information into collections by types, the types including at least one of segments, equipment, ports, or connections;

means for positioning the components for presentation of a circuit design on a display based on the circuit information received from the backend circuit test system, where

positioning the components comprises positioning each piece of equipment within one or more segments, and

positioning each piece of equipment within one or more segments comprises adding non-visible elements to force distribution of equipment around the one or more segments;

means for rendering the circuit design based on the positioning of the components; and

means for sending an output file with the rendering to a web browser.

11. The device of claim 10 , where at least one segment, of the one or more segments, comprises a synchronous optical networking (SONET) ring.

12. The device of claim 10 , where positioning the components comprises:

following interconnectivity of the components in sequence to identify one or more segments,

assigning each segment to a logical column,

positioning each segment within the logical column, and

positioning each port on one of each piece of equipment.

13. The device of claim 12 , where the number of segments in the logical column is optimized according to a rule set that advances a segment from an assigned default column to a preceding column.

14. The device of claim 12 , where both a clockwise orientation and a counterclockwise orientation of SONET rings are used to prevent connections from crossing.

15. A method, comprising:

receiving, by at least one device, circuit information from a backend circuit test system;

grouping, by the at least one device, components in the circuit information into collections by types, said grouping comprising identifying each component as one of a segment, equipment, a port, or a connection;

positioning, by the at least one device and based on the grouping by types, the components from the circuit information for presentation of a circuit design on a display, where

positioning the components comprises assigning each segment to a logical column, and

assigning each segment to a logical column comprises traversing each segment using a width-first n-array tree traversal based on the connectivity associated with each of the segments;

performing, by the at least one device, path rendering for the circuit design based on the positioning of the components; and

sending, by the at least one device, an output file with the path rendering to a web browser.

16. The method of claim 15 , where a number of segments in the logical column is optimized according to a rule set that advances a segment from an assigned default column to a preceding column.

17. The method of claim 15 , where

positioning the components comprises positioning each piece of equipment within one or more segments, and

positioning each piece of equipment within one or more segments comprises adding non-visible elements to force distribution of equipment around the one or more segments.

18. The method of claim 15 , where

positioning the components comprises positioning each port on one of each piece of equipment, and

positioning each port on one of each piece of equipment comprises defining a best edge of each piece of equipment, where the best edge includes an edge that minimizes overlap of a connection with other components.

19. A non-transitory computer-readable medium comprising:

one or more instructions which, when executed by at least one processor, cause the at least one processor to receive circuit information from a backend circuit test system;

one or more instructions which, when executed by at least one processor, cause the at least one processor to group components in the circuit information into collections by types, said grouping comprising identifying each component as one of a segment, equipment, a port, or a connection;

one or more instructions which, when executed by at least one processor, cause the at least one processor to position, based on the grouping by types, the components from the circuit information for presentation of a circuit design on a display, where

positioning the components comprises assigning each segment to a logical column and positioning each segment within the logical column, and

the number of segments in the logical column is optimized according to a rule set that advances a segment from an assigned default column to a preceding column;

one or more instructions which, when executed by at least one processor, cause the at least one processor to perform path rendering for the circuit design based on the positioning of the components; and

one or more instructions which, when executed by at least one processor, cause the at least one processor to send an output file with the path rendering to a web browser.

20. The non-transitory computer-readable medium of claim 19 , where the one or more instructions which, when executed by at least one processor, cause the at least one processor to the components include one or more instructions to:

follow interconnectivity of the components in sequence to identify one or more segments,

position each piece of equipment within one or more segments, and

position each port on one of each piece of equipment.

21. The non-transitory computer-readable medium of claim 20 , where the one or more instructions to position each port on one of each piece of equipment include one or more instructions to:

define a best edge of each piece of equipment, where the best edge includes an edge that minimizes overlap of a connection with other components.

22. The non-transitory computer-readable medium of claim 19 , where both a clockwise orientation and a counterclockwise orientation of SONET rings are used to prevent connections from crossing.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2009
From: VERIZON DATA SERVICES LLC
To: VERIZON PATENT AND LICENSING INC.
Reel/Frame 023112/0047 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2008
From: SCHULMISTER, JOSEPH DAVID, JR.
To: VERIZON DATA SERVICES LLC
Reel/Frame 021563/0791 →