Digital-to-analog converter

1. A converter for converting an N-bit digital signal (N is an integer of three or more) into an analog signal using a plurality of different reference voltages, comprising:

a selection voltage divider circuit having a plurality of MOS transistors each functioning as a switch, wherein the selection voltage divider circuit selects two of the plurality of reference voltages via respective sets of MOS transistors of the plurality of MOS transistors, the sets having the same number of MOS transistors, in accordance with the (N−m) most significant bits of the digital signal, and divides a difference between the two selected reference voltages into M by combined ON-resistances of M MOS transistor groups connected in series of the plurality of MOS transistors to obtain (M−1) intermediate voltages, where m is an integer of one or more and M is an integer of 2 m to 2 m−1 +1;

a mode selection circuit for determining a magnitude of the combined ON-resistance of each of the M MOS transistor groups of the selection voltage divider circuit, selecting a first mode when the combined ON-resistance is large and a second mode when the combined ON-resistance is small, and performing a control so that the number of MOS transistors included in each of the M MOS transistor groups in the selection voltage divider circuit is larger in the second mode than in the first mode; and

an output circuit for selectively outputting one of the two selected reference voltages or one of the (M−1) intermediate voltages as the analog signal in accordance with the m least significant bits of the digital signal.

2. The converter of claim 1 , further comprising:

a reference voltage generating circuit for generating the plurality of reference voltages,

wherein the reference voltage generating circuit has 2 N−m resistors connected in series, and supplies (2 N−m +1) different reference voltages from terminals of the resistors to the selection voltage divider circuit.

3. The converter of claim 1 , wherein

the selection voltage divider circuit has a switch circuit for selecting two adjacent reference voltages from the plurality of reference voltages.

4. The converter of claim 3 , wherein

the switch circuit has a plurality of switch pairs, wherein each of the plurality of switch pairs selects one of two inputs in accordance with a corresponding bit of the (N−m) most significant bits of the digital signal,

the number a n of switch pairs corresponding to the n-th bit counted from the least significant bit of the (N−m) most significant bits of the digital signal is represented by:

a 1 =2, a n =a n−1 +2 n−2 (2≦ n≦N−m ), and

the two adjacent reference voltages are selected via (N−m) of MOS transistors included in the plurality of switch pairs.

5. The converter of claim 4 , wherein

each of the M MOS transistor groups in the selection voltage divider circuit has (N−m+1) or more MOS transistors connected in series, and

two of the M MOS transistor groups each include the (N−m) MOS transistors for selecting the two adjacent reference voltages, in the (N−m+1) or more MOS transistors connected in series.

6. The converter of claim 3 , wherein

the selection voltage divider circuit further has a decoding circuit for decoding P least significant bits of the (N−m) most significant bits of the digital signal into 2 P selection signals any one of which is valid, where P is an integer of 2 or more and (N−m) or less,

the switch circuit has:

2 P switch pairs each for selectively transferring two inputs to two outputs in accordance with a corresponding one of the 2 P selection signals; and

a plurality of other switch pairs each for selecting one of two inputs in accordance with a corresponding one of the (N−m−P) most significant bits of the digital signal, and

the two adjacent reference voltages are each selected via (N−m−P+1) of MOS transistors included in all the switch pairs.

7. The converter of claim 6 , wherein

each of the M MOS transistor groups of the selection voltage divider circuit has (N−m−P+2) or more MOS transistors connected in series, and

two of the M MOS transistor groups each include (N−m−P+1) MOS transistors for selecting the two adjacent reference voltages in the (N−m−P+2) or more MOS transistors connected in series.

8. The converter of claim 1 , where

the number of MOS transistors included in each of the M MOS transistor groups in the selection voltage divider circuit is set so that combined ON-resistances of the M MOS transistor groups are equal to each other.

9. The converter of claim 1 , where

the MOS transistors included in each of the M MOS transistor groups in the selection voltage divider circuit each have a size that is set so that combined ON-resistances of the M MOS transistor groups are equal to each other.

10. An image display device comprising a display panel having a plurality of pixels and a drive circuit for driving the plurality of pixels in accordance with a digital signal indicating a gray level of an image, wherein

the drive circuit includes:

a reference voltage generating circuit for generating a plurality of different reference voltages; and

a plurality of digital-to-analog converters for converting the digital signal indicating the gray level of the image into an analog signal for each pixel column using the plurality of reference voltages,

each of the plurality of digital-to-analog converters is the converter of claim 1 .

11. The image display device of claim 10 , wherein

the reference voltage generating circuit has a plurality of resistance voltage divider circuits for sharing a load of supplying reference voltages to a portion of the converters for each pixel column.