Minimizing plating stub reflections in a chip package using capacitance
View Patent ↗Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.
1. A multi-layer substrate for interfacing a chip with a printed circuit board, comprising:
a first outer layer providing a chip mounting location, a signal interconnect spaced from the chip mounting location, a signal trace extending from near the chip mounting location to the signal interconnect, and a plating stub extending from the signal interconnect;
a ground layer; and
a capacitor coupling the plating stub to the ground layer.
2. The multi-layer substrate of claim 1 , wherein the capacitor comprises a discrete capacitor secured to the first outer layer, the discrete capacitor including a first lead electrically connected to the plating stub and a second lead electrically connected to the ground layer.
3. The multi-layer substrate of claim 1 , wherein the capacitor is embedded within the multi-layer substrate.
4. The multi-layer substrate of claim 3 , wherein the capacitor embedded within the multi-layer substrate comprises:
a first capacitor plate formed in the ground layer; and
a second capacitor plate formed in another layer spaced from the ground layer.
5. The multi-layer substrate of claim 3 , wherein the second capacitor plate is formed in a power layer.
6. The multi-layer substrate of claim 1 , further comprising a via concentric with and in electrical communication with the signal interconnect.
7. The multi-layer substrate of claim 6 , further comprising:
a second outer layer opposite the first outer layer, wherein the via extends from the first outer layer to the second outer layer; and
a ball of a ball grid array connected with the via on the second outer layer.
8. A chip package, comprising:
a multi-layer substrate having a first outer face and an opposing second outer face;
a chip secured to the first face of the substrate;
a signal interconnect along the first face of the substrate, a signal trace electrically connecting the chip to the signal interconnect, a plating stub extending outwardly from the signal interconnect, and a capacitor connecting the plating stub to ground; and
an electrical contact disposed along the first or second face and configured for mating with a corresponding electrical contact on a printed circuit board.
9. The chip package of claim 8 , wherein the electrical contact disposed along the first or second face comprises a ball of a ball grid array.
10. The chip package of claim 8 , further comprising a bond wire electrically connecting the chip to the signal trace.
11. The chip package of claim 8 , wherein the capacitor comprises a discrete capacitor secured to the first outer face, the discrete capacitor including a first lead electrically connected to the plating stub and a second lead electrically connected to a ground layer in the multi-layer substrate.
12. The chip package of claim 8 , wherein the capacitor is embedded within the multi-layer substrate.
13. The chip package of claim 12 , wherein the capacitor embedded within the multi-layer substrate comprises:
a first capacitor plate formed in the ground layer; and
a second capacitor plate formed in another layer spaced from the ground layer.
14. The chip package of claim 12 , wherein the second capacitor plate is formed in a power layer of the multi-layer substrate.