High speed serial link with power spectral density frequency response suppression
View Patent ↗This disclosure relates to noise suppression in data transfers in transceivers of wireless devices.
1. A baseband component of a transceiver comprising:
an input/output (IO) interface that receives data signals;
a digital signal processor (DSP) that receives the data signals from the IO interface, limits the bandwidth of the data signal forming an equivalent low pass signal or baseband signal that is further transmitted using multi-bit parallel data link; and
a baseband interface that converts data associated with the multi-bit parallel data link to serial data, or serial data to multi-bit parallel data link data, that comprises a filter that filters unwanted noise from the data signals, and produces a filtered baseband signal.
2. The baseband component of claim 1 , wherein the IO interface receives analog signals, and converts the analog signals to digital signals.
3. The baseband component of claim 1 , wherein the filter is a mix digital analog filter that contains serial digital bit streams input and analog output.
4. The baseband component of claim 1 , wherein the filter is a Finite Impulse Response (FIR) filter.
5. The baseband component of claim 1 , wherein the FIR filter is one of the following: a zeroing/attenuating FIR filter, a boosting FIR filter, or an amplifying FIR filter.
6. The baseband component of claim 1 , wherein the FIR filter includes a finite number of impulse responses corresponding to a finite number of sample intervals.
7. The baseband component of claim 1 , wherein the FIR filter includes delays to create a desired amplitude response of the filtered signal.
8. The baseband component of claim 1 , wherein the baseband interface is a digital interface connected to the RF component by two way serial link.
9. A digital interface component comprising:
a baseband interface that converts multi-bit parallel data link data into serial data when transmitting data signals, and converts serial data to multi-bit parallel data link data when receiving data signals;
a signal interface that links the baseband interface and the radio frequency interface for concurrent serial bi-directional communication; and
a radio frequency (RF) interface that receives data signals from the signal interface.
10. The digital interface of claim 9 , wherein the baseband interface and the RF interface include Finite Impulse Response (FIR) filters that inserts zero or attenuate Power Spectral Density causing Radio Frequency Interface.
11. The digital interface of claim 9 , wherein the signal interface comprises a six wire interface.
12. The digital interface of claim 9 , further comprising a system clock line and a clock enable line to provide timing references for digital serial data transmission and recovery.
13. A method of transmitting data signals comprising:
receiving the data signals;
transforming the data signals into codewords and mapping the data signals into attributes wherein the data signals is carried in a multi-bit parallel data link entering the digital signal processor;
converting the data signals associated with the multi-bit parallel data link into a one bit serial data signal; and
filtering the serial data signal of unwanted noise into a filtered data signal.
14. The method of claim 13 , wherein the receiving includes converting analog signals into digital signals.
15. The method of claim 13 , wherein the filtering includes reshaping the data signals to remove the unwanted noise.
16. The method of claim 13 , further comprising modulating the filtered data signals with a carrier frequency to produce modulated RF signal.