Information processing apparatus and SMI processing method thereof

1. An information processing apparatus comprising:

a CPU;

a bridge circuit, comprising a north bridge portion and a south bridge portion, the bridge circuit connected to the CPU via a first bus, the bridge circuit including a signal transmission unit configured to supply a system management interrupt (SMI) signal to the CPU;

a single multifunction device connected to the bridge circuit via a second bus, the single multifunction device having a plurality of functions each configured to cause an SMI event; and

a register configured to store pieces of information, in which each piece of information corresponds to one of the plurality of functions and the information identifies a trigger function for the SMI event.

2. The information processing apparatus of claim 1 , wherein the register is incorporated in the bridge circuit.

3. The information processing apparatus of claim 1 , further comprising an SMI processing unit configured to acquire the information held in the register to determine whether the SMI event associated with the multifunction device occurs when the SMI signal is supplied from the bridge circuit to the CPU.

4. The information processing apparatus of claim 1 , further comprising a plurality of signal lines provided between the bridge circuit and the multifunction device, each of the signal lines corresponding to one of the plurality of functions of the multifunction device and configured to send a notification of occurrence of an SMI event from the multifunctional device to the bridge circuit.

5. The information processing apparatus of claim 1 , wherein the first bus operates at a higher communication speed than the second bus.

6. An information processing apparatus comprising:

a CPU;

a bridge circuit, comprising a north bridge portion and a south bridge portion, the bridge circuit connected to the CPU via a first bus, the bridge circuit including a signal transmission unit configured to supply a system management interrupt(SMI) signal to the CPU;

a single multifunction device connected to the bridge circuit via a second bus, the single multifunction device having a plurality of functions each configured to cause an SMI event;

a plurality of signal lines of the second bus provided between the bridge circuit and the multifunction device, each of the signal lines corresponding to one of the plurality of functions of the multifunction device and configured to send a notification of occurrence of the SMI event from the multifunction device to the bridge circuit; and

wherein the bridge circuit includes a register that is configured to store pieces of information, in which each piece of information corresponds to one of the plurality of functions and the information identifies a trigger function for the SMI event.

7. The information processing apparatus of claim 6 , further comprising an SMI processing unit configured to acquire the information held in the register to determine whether an SMI event associated with the multifunction device occurs when the SMI signal is supplied from the bridge circuit to the CPU.

8. The information processing apparatus of claim 6 , wherein the first bus operates at a higher communication speed than the second bus.

9. An information processing apparatus comprising:

a CPU;

a bridge circuit, comprising a north bridge portion and a south bridge portion, the bridge circuit connected to the CPU via first bus, the bridge circuit including a signal transmission unit configured to supply a system management interrupt (SMI) signal to the CPU, the bridge circuit configured to cause a given SMI event;

a single multifunction device connected to the bridge circuit via a second bus and a plurality of signal lines, the single multifunction device having a plurality of functions each configured to cause an SMI event; and

a register configured to store pieces of information, in which each piece of information corresponds to one of the plurality of functions and the information identifies a trigger function for the SMI event.

10. The information processing apparatus of claim 9 , further comprising:

an SMI processing unit configured to access to the bridge circuit to determine whether the given SMI event is caused by the bridge circuit and to acquire the information held in the register to determine whether the SMI event associated with the multifunction device occurs when the SMI signal is supplied from the bridge circuit to the CPU.

11. The information processing apparatus of claim 9 ,

wherein the plurality of signal lines are provided between the bridge circuit and the multifunction device; and

each of the signal lines corresponds to one of the plurality of functions of the multifunction device and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the bridge circuit.

12. The information processing apparatus of claim 9 , wherein the register is incorporated in the bridge circuit.

13. The information processing apparatus of claim 9 , wherein the first bust operates at a higher communication speed than the second bus.

14. An information processing apparatus comprising:

a CPU;

a bridge circuit, comprising a north bridge portion and a south bridge portion that are interconnected via a link bus, the north bridge portion of the bridge circuit being connected to the CPU via a first bus, the south bridge portion including a signal transmission unit configured to supply a system management interrupt (SMI) signal to the CPU;

a single multifunction device connected to the south bridge portion of the bridge circuit via a second bus, the single multifunction device configured to perform a plurality of functions in which each of the functions are configured to initiate an SMI event and generate an SMI signal, the generated SMI signal being submitted to the north bridge portion via the link bus and reported to the CPU via the first bus; and

a register configured to store pieces of information, in which each piece of information corresponds to one of the plurality of functions performed by the single multifunction device and each piece of information identifies a trigger function for the SMI event.

15. The information processing apparatus of claim 14 , further comprising an SMI processing unit configured to acquire the information held in the register to determine whether the SMI event associated with the single multifunction device occurs when the SMI signal is supplied from the south bridge portion to the CPU.

16. The information processing apparatus of claim 14 , further comprising a plurality of signal lines provided between the south bridge portion and the signal multifunction device, each of the signal lines corresponding to one of the plurality of functions of the single multifunction device and configured to send a notification of occurrence of an SMI event from the multifunctional device to the south bridge portion.

17. The information processing apparatus of claim 14 , wherein the first bus operates at a higher communication speed than the second bus.