System and method for high temperature compact thermoelectric generator (TEG) device construction
View Patent ↗A method for creating an array of thermoelectric elements includes applying a first coating of dielectric material to P-type wafers and N-type wafers to form coated P-type wafers and coated N-type wafers. A P/N-type ingot is formed from the coated P-type wafers and the coated N-type wafers. The coated P-type wafers and the coated N-type wafers are alternatingly arranged in the P/N-type ingot. P/N-type wafers comprising P-type elements and N-type elements are sliced from the P/N-type ingot and a second coating of the dielectric material is applied to the P/N-type wafers to form coated P/N-type wafers. Furthermore, a P/N-type array from the coated P/N-type wafers.
1. A method for creating an array of thermoelectric elements, comprising:
applying a first coating of dielectric material to P-type wafers and N-type wafers to form coated P-type wafers and coated N-type wafers;
forming a P/N-type ingot from the coated P-type wafers and the coated N-type wafers, the coated P-type wafers and the coated N-type wafers alternatingly arranged in the P/N-type ingot;
slicing from the P/N-type ingot, P/N-type wafers comprising P-type elements and N-type elements;
applying a second coating of dielectric material to the P/N-type wafers to form coated P/N-type wafers; and
forming a P/N-type array from the coated P/N-type wafers, wherein the second coating of dielectric material is operable to electrically insulate adjacent elements in the P/N-type array from one another.
2. The method of claim 1 , further comprising removing the dielectric material from a top surface and a bottom surface of the P/N-type array to expose faces of the P-type elements and the N-type elements.
3. The method of claim 2 , further comprising trimming the P/N-type array to shorten the P-type elements and the N-type elements to a desired length.
4. The method of claim 3 , further comprising forming a thermoelectric device from the P/N-type array by applying electrical interconnects to the faces of the P-type elements and the N-type elements.
5. The method of claim 4 , further comprising applying a third coating of dielectric material to the thermoelectric device.
6. The method of claim 1 , wherein forming a P/N-type ingot comprises:
applying adhesive to the coated P-type wafers and the coated N-type wafers;
stacking the coated P-type wafers and the coated N-type wafers in an alternating relationship;
pressing the coated P-type wafers and the coated N-type wafers together to decrease widths of first bond lines between coated P-type wafers and the coated N-type wafers; and
curing the adhesive to form the P/N-type ingot.
7. The method of claim 6 , comprising pressing the coated P-type wafers and the coated N-type wafers together until the coated P-type wafers and the coated N-type wafers touch one another along the first bond lines.
8. The method of claim 1 , wherein forming a P/N-type array from the P/N-type wafers, comprises:
applying adhesive to the coated P/N-type wafers;
stacking the coated P/N-type-wafers;
pressing the coated P/N-type wafers together to decrease widths of second bond lines between coated P/N-type wafers;
curing the adhesive to form a P/N-type block; and
slicing the P/N-type array from the P/N-type block.
9. The method of claim 8 , comprising pressing the coated P/N-type wafers together until the coated P/N-type wafers touch one another along the second bond lines.
10. The method of claim 9 , further comprising removing any excess adhesive that is squeezed out of the first bond lines or the second bond lines.
11. The method of claim 1 , wherein the dielectric material comprises a high temperature dielectric material adapted to withstand a full range of operating temperatures produced by a thermoelectric device built from the thermoelectric array.
12. The method of claim 1 , wherein the first coating is uniform in thickness.
13. The method of claim 1 , wherein the second coating is uniform in thickness.
14. The method of claim 1 , wherein the first coating is equal in thickness to the second coating.
15. The method of claim 1 , further comprising arranging the P/N-type wafers such that the P-type elements and the N-type elements form a checkerboard pattern in the P/N-type array.
16. The method of claim 1 , wherein each coated wafer of the coated P-type wafers and the coated N-type wafers is uniform in dimension to every other coated wafer of the coated P-type wafers and the coated N-type wafers.
17. The method of claim 1 , wherein each coated wafer of the coated P/N-type wafers is uniform in dimension to every other coated wafer of the coated P/N-type wafers.
18. A method for creating an array of thermoelectric elements, comprising:
applying a first coating of dielectric material to P-type wafers and N-type wafers to form coated P-type wafers and coated N-type wafers;
applying adhesive to the coated P-type wafers and the coated N-type wafers;
stacking the coated P-type wafers and the coated N-type wafers in an alternating relationship;
pressing the coated P-type wafers and the coated N-type wafers together to decrease widths of first bond lines between coated P-type wafers and the coated N-type wafers; and
curing the adhesive to form the P/N-type ingot, the coated P-type wafers and the coated N-type wafers alternatingly arranged in the P/N-type ingot;
slicing from the P/N-type ingot, P/N-type wafers comprising P-type elements and N-type elements;
applying a second coating of dielectric material to the P/N-type wafers to form coated P/N-type wafers; and
applying adhesive to the coated P/N-type wafers;
stacking the coated P/N-type-wafers;
pressing the coated P/N-type wafers together to decrease widths of second bond lines between coated P/N-type wafers;
curing the adhesive to form a P/N-type block, the P/N-type block comprising the P-type elements and the N-type elements.
19. The method of claim 18 , comprising pressing the coated P/N-type wafers together until the coated P/N-type wafers touch one another along the second bond lines.
20. A method for creating an array of thermoelectric elements, comprising:
first applying a first coating of dielectric material to P-type wafers and N-type wafers to form coated P-type wafers and coated N-type wafers;
second forming a P/N-type ingot from the coated P-type wafers and the coated N-type wafers, the coated P-type wafers and the coated N-type wafers alternatingly arranged in the P/N-type ingot;
third slicing from the P/N-type ingot, P/N-type wafers comprising P-type elements and N-type elements;
fourth applying a second coating of dielectric material to the P/N-type wafers to form coated P/N-type wafers; and
fifth forming a P/N-type array from the coated P/N-type wafers, wherein:
the second coating of dielectric material is operable to electrically insulate adjacent elements in the P/N-type array from one another; and
the steps are performed in the order in which they are numbered.
21. The method of claim 1 , wherein each wafer of the P-type wafers and N-type wafers comprises a first flat face disposed opposite a second flat face, the first and second flat faces surrounded by a common, narrow edge.