System and method for improving dynamic response in a power supply

1. A system for improving dynamic response in a power supply, comprising:

a mainframe module having a memory and a mainframe microprocessor, the mainframe processor configured to calculate a plurality of tables in which each table represents a current/voltage (I/V) characteristic curve for the power supply;

at least two power supply modules coupled to the mainframe module, each power supply module having a random access memory element, the random access memory element configured to receive and store a first table and a second table;

wherein the mainframe microprocessor transfers the first table to each power supply module, and wherein each power supply module executes a respective first table while the mainframe processor calculates the second table for each power supply module and while the mainframe processor transfers the second table to each power supply module.

2. The system of claim 1 , in which the random access memory element comprises a dual-port structure, wherein a first port is configured to receive the first table and wherein a second port is configured to execute the first table while the first port is receiving the second table.

3. The system of claim 2 , in which the random access memory element further comprises an additional memory block configured to store at least one filter coefficient.

4. The system of claim 3 , further comprising:

a timing element having a magnitude comparator configured to receive an output voltage signal that is representative of the voltage output of at least one of the power supply modules and configured to receive a table voltage value that corresponds to voltage data stored in the random access memory element at an address location identified by a successive approximation register;

the magnitude comparator configured to compare the output voltage signal with the table voltage value to determine a point at which the table voltage value just exceeds the output voltage signal; and

wherein the address location represents a scaled current value that corresponds to the output voltage signal.

5. The system of claim 4 , further comprising a lowpass filter configured to receive the filter coefficient from the additional memory block, in which the filter coefficient is obtained from the address location.

6. The system of claim 5 , in which the first table and the second table comprise 4096 address locations each having a table voltage value.

7. The system of claim 5 , in which the first table and the second table comprise 256 address locations each having a table voltage value.

8. A method for improving dynamic response in a power supply, comprising:

calculating a first table for each of at least two power supply modules, in which each first table represents a current/voltage (I/V) characteristic curve for the power supply;

transferring the first table to the at least two power supply modules;

executing the first table in each of the at least two power supply modules;

simultaneously with the execution of the first table in each of the at least two power supply modules, calculating a second table for each of the at least two power supply modules;

simultaneously with the execution of the first table in each of the at least two power supply modules, transferring the second table to the at least two power supply modules;

executing the second table in each of the at least two power supply modules; and

simultaneously with the execution of the second table in each of the at least two power supply modules, calculating a revised first table for each of the at least two power supply modules.

9. The method of claim 8 , in which transferring the first and second tables further comprises transferring the first and second tables to a first port of a dual-port random access memory element.

10. The method of claim 9 , in which executing the first and second tables further comprises executing the first and second tables from a second port of the dual-port random access memory element.

11. The method of claim 10 , in which the random access memory element further comprises an additional memory block configured to store at least one filter coefficient.

12. The method of claim 11 , further comprising;

receiving in a timing element an output voltage signal that is representative of the voltage output of at least one of the power supply modules;

receiving in the timing element a table voltage value that corresponds to voltage data stored in the random access memory element at an address location identified by a successive approximation register; and

comparing the output voltage signal with the table voltage value to determine a point at which the table voltage value just exceeds the output voltage signal, wherein the address location represents a scaled current value that corresponds to the output voltage signal.

13. The method of claim 12 , further comprising:

receiving in a lowpass filter the filter coefficient from the additional memory block, in which the filter coefficient is obtained from the address location.

14. The method of claim 13 , in which the first table and the second table comprise 4096 address locations each having a table voltage value.

15. The method of claim 13 , in which in which the first table and the second table comprise 256 address locations each having a table voltage value.

16. A system for improving dynamic response in a power supply, comprising:

a mainframe module having a memory and a mainframe microprocessor, the mainframe processor configured to calculate a plurality of tables in which each table represents a current/voltage (I/V) characteristic curve for the power supply;

at least one power supply module coupled to the mainframe module, the power supply module having a random access memory element, the random access memory element configured to receive and store a first table and a second table;

wherein the mainframe microprocessor transfers the first table to the power supply module, and wherein the power supply module executes the first table while the mainframe processor calculates the second table for the power supply module and while the mainframe processor transfers the second table to the power supply module.

17. The system of claim 16 , in which the random access memory element comprises a dual-port structure, wherein a first port is configured to receive the first table and wherein a second port is configured to execute the second table while the first port is receiving an updated first table.

18. The system of claim 17 , in which the random access memory element further comprises an additional memory block configured to store at least one filter coefficient.

19. The system of claim 18 , further comprising:

a timing element having a magnitude comparator configured to receive an output voltage signal that is representative of the voltage output of the at least one of the power supply module and configured to receive a table voltage value that corresponds to voltage data stored in the random access memory element at an address location identified by a successive approximation register;

the magnitude comparator configured to compare the output voltage signal with the table voltage value to determine a point at which the table voltage value just exceeds the output voltage signal; and

wherein the address location represents a scaled current value that corresponds to the output voltage signal.

20. The system of claim 19 , further comprising a lowpass filter configured to receive the filter coefficient from the additional memory block, in which the filter coefficient is obtained from the address location.

21. The system of claim 19 , further comprising a successive approximation register configured to determine the address location, where the address location has a non-linear relationship with the output voltage value.