Ripple preventing gate driving circuit and display apparatus having the same
View Patent ↗A gate driving circuit includes stages, the stages being cascaded and each including: a pull-up part which pulls up a gate voltage to a clock signal during a horizontal scanning period (1H); a carry part which pulls up a carry voltage to the clock signal during the horizontal scanning period (1H); a pull-up driving part connected to a control terminal (Q-node) common to the carry part and the pull-up part and which receives a previous carry voltage from a first previous stage to turn on the pull-up part and the carry part; and a ripple preventing part which prevents a ripple generated at a previous Q-node of a second previous stage based on a ripple generated at the Q-node of the carry part and the pull-up part.
1. A gate driving circuit comprising stages, the stages being cascaded with each other and each comprising:
a pull-up part which pulls up a gate voltage to a clock signal in response to a control voltage of a control terminal (Q-node) of the pull-up part during a horizontal scanning period (1H);
a carry part which pulls up a carry voltage to the clock signal in response to the control voltage of the Q-node during the horizontal scanning period (1H), the Q-node being connected to a control electrode of the carry part;
a pull-up driving part connected to the Q-node common to the carry part and the pull-up part and which receives a previous carry voltage from a first previous stage and outputs the control voltage to the Q-node; and
a ripple preventing part that includes a control electrode directly connected to the Q-node common to the carry part and the pull-up part, wherein the ripple preventing part prevents a ripple generated at a previous Q-node of a second previous stage based on a ripple generated at the Q-node of the carry part and the pull-up part.
2. The gate driving circuit of claim 1 , wherein
the Q-node of the carry part and the pull-up part is an i-th Q-node disposed in an i-th stage,
the Q-node of the second previous stage is an (i−2)th Q-node disposed in an (i−2)-th stage, and
i is a natural number greater than or equal to 3.
3. The gate driving circuit of claim 2 , wherein
the i-th stage further comprises a voltage input terminal to which a ground voltage is applied, and
the ripple preventing part electrically connects the (i−2)-th Q-node and the voltage input terminal based on a ripple generated at the i-th Q-node to discharge a ripple generated at the (i−2)-th Q-node to the ground voltage.
4. The gate driving circuit of claim 2 , wherein the i-th stage further comprises:
a holding part which holds the pull-up part and the carry part in a turn-off state; and
an inverter which operates so as to perform one of turn on the holding part and turn off the holding part based on the clock signal.
5. The gate driving circuit of claim 4 , wherein the holding part comprises a holding transistor comprising:
a control electrode connected to an output terminal of the inverter;
an input electrode which receives the ground voltage; and
an output electrode connected to an output terminal of the pull-up driving part.
6. The gate driving circuit of claim 3 , wherein the ripple preventing part comprises a ripple discharge transistor comprising:
a control electrode electrically connected to the i-th Q-node;
an input electrode electrically connected to the voltage input terminal; and
an output electrode electrically connected to the (i−2)-th Q-node.
7. The gate driving circuit of claim 6 , wherein the pull-up part comprises a pull-up transistor comprising:
a control electrode connected to the i-th Q-node;
an input electrode which receives the clock signal; and
an output electrode which outputs the gate voltage as an i-th gate voltage,
wherein a ratio of a channel width to a channel length of the ripple discharge transistor is less than a ratio of a channel width to a channel length of the pull-up transistor.
8. The gate driving circuit of claim 7 , wherein the carry part comprises:
a carry transistor comprising:
a control electrode connected to the i-th Q-node;
an input electrode which receives the clock signal; and
an output electrode which outputs the carry voltage; and
a first capacitor connected between the control electrode and the output electrode of the carry transistor.
9. The gate driving circuit of claim 7 , further comprising a pull-down part which discharges the i-th gate voltage to the ground voltage based on an (i+1)-th gate voltage from an (i+1)-th stage.
10. The gate driving circuit of claim 9 , wherein the pull-down part comprises:
a first pull-down transistor comprising:
a control electrode which receives the (i+1)-th gate voltage;
an input electrode connected to the voltage input terminal; and
an output electrode connected to an output terminal of the pull-up part; and
a second pull-down transistor comprising:
a control electrode which receives the (i+1)-th gate voltage;
an input electrode connected to the voltage input terminal; and
an output electrode connected to the i-th Q-node.
11. The gate driving circuit of claim 10 , wherein a ratio of a channel width to a channel length of the second pull-down transistor is approximately equal to the ratio of the channel width to the channel length of the ripple discharge transistor.
12. The gate driving circuit of claim 8 , wherein the pull-up driving part comprises:
a buffer transistor comprising:
an input electrode which receives a previous carry voltage from an (i−1)-th stage;
a control electrode which receives the previous carry voltage from the (i−1)-th stage; and
an output electrode connected to the i-th Q-node; and
a second capacitor connected between the control electrode and the output electrode of the pull-up transistor.
13. A display apparatus comprising:
a display part which displays an image based on a gate signal and a data signal;
a data driving circuit which applies the data signal to the display part; and
a gate driving circuit comprising stages to sequentially apply the gate signal to the display part, the stages being cascaded with each other and each of the stages comprising:
a pull-up part which pulls up a gate voltage to a clock signal in response to a control voltage of a control terminal (Q-node) of the pull-up part during a horizontal scanning period (1H);
a carry part which pulls up a carry voltage to the clock in response to the control voltage of the Q-node during the horizontal scanning period (1H)), the Q-node being connected to a control electrode of the carry part;
a pull-up driving part connected to the Q-node common to the carry part and the pull-up part and which receives a previous carry voltage from a first previous stage and outputs the control voltage to the Q-node; and
a ripple preventing part that includes a control electrode directly connected to the Q-node common to the carry part and the pull-up part, wherein the ripple preventing part prevents a ripple generated at a previous Q-node of a second previous stage based on a ripple generated at the Q-node of the carry part and the pull-up part.
14. The display apparatus of claim 13 , wherein
the Q-node of the carry part and the pull-up part is an i-th Q-node disposed in an i-th stage,
the Q-node of the second previous stage is an (i−2)-th Q-node disposed in an (i−2)-th stage, and
i is a natural number greater than or equal 3.
15. The display apparatus of claim 14 , wherein
the i-th stage further comprises a voltage input terminal to which a ground voltage is applied, and
the ripple preventing part electrically connects the (i−2)-th Q-node and the voltage input terminal based on a ripple generated at the i-th Q-node to discharge a ripple generated at the (i−2)-th Q-node to the ground voltage.
16. The display apparatus of claim 15 , wherein the ripple preventing part comprises a ripple discharge transistor comprising:
a control electrode electrically connected to the i-th Q-node;
an input electrode electrically connected to the voltage input terminal; and
an output electrode electrically connected to the (i−2)-th Q-node.
17. A method for driving a gate driving circuit comprising cascaded stages, the method comprising:
pulling up a gate voltage to a clock signal during a horizontal scanning period (1H) using a pull-up part including a control terminal (Q-node);
pulling up a carry voltage to the clock signal during the horizontal scanning period (1H) using a carry part including a control electrode connected to the Q-node;
receiving a previous carry voltage from a first previous stage with a pull-up driving part connected to the Q-node common to the carry part and the pull-up part to turn on the pull-up part and the carry part; and
preventing a ripple generated at a previous Q-node of a second previous stage based on a ripple generated at the Q-node of the carry part and the pull-up part using a ripple preventing part including a control electrode directly connected to the Q-node common to the carry part and the pull-up part.
18. The method of claim 17 , wherein
the Q-node of the carry part and the pull-up part is an i-th Q-node disposed in an i-th stage,
the Q-node of the second previous stage is an (i−2)-th Q-node disposed in an (i−2)-th stage, and
i is a natural number greater than or equal 3.