IP Library Granted Patent US 7,851,871
Granted Patent B2
US 7,851,871 · App. 12/242,142 · Granted Dec 14, 2010

Semiconductor device and method for fabricating the same

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Quick Facts
Patent No.
US 7,851,871
App. No.
12/242,142
Granted
Dec 14, 2010
Kind
B2
Abstract

A high-voltage transistor and a peripheral circuit including a second conductivity type MOSFET are provided together on a first conductivity type semiconductor substrate. The high-voltage transistor includes: a low concentration drain region of a second conductivity type formed in the semiconductor substrate; a low concentration source region of a second conductivity type formed in the semiconductor substrate and spaced apart from the low concentration drain region; and a high concentration source region of a second conductivity type having a diffusion depth deeper than that of the low concentration source region. A diffusion depth of the low concentration source region is equal to that of source/drain regions of the MOSFET.

Claims (12)

1. A semiconductor device comprising a first conductivity type semiconductor substrate, a high-voltage transistor and a peripheral circuit which includes a second conductivity type MOSFET, the high-voltage transistor and the peripheral circuit being provided together on the first conductivity type semiconductor substrate,

wherein the high-voltage transistor includes:

a low concentration drain region of a second conductivity type formed in the semiconductor substrate;

a low concentration source region of a second conductivity type formed in the semiconductor substrate and spaced apart from the low concentration drain region;

a high concentration source region of a second conductivity type formed in part of the semiconductor substrate that is between the low concentration drain region and the low concentration source region, the high concentration source region being spaced apart from the low concentration drain region and adjacent to the low concentration source region and having a diffusion depth deeper than that of the low concentration source region;

a gate electrode formed above the semiconductor substrate between the low concentration drain region and the high concentration source region so as to be insulated from the semiconductor substrate;

a high concentration drain region of a second conductivity type formed in the low concentration drain region;

a drain electrode formed on the semiconductor substrate so as to connect to the high concentration drain region;

a substrate contact region of a first conductivity type formed so as to be at least in contact with a lower interface of the low concentration source region; and

a source electrode formed on the semiconductor substrate so as to connect to the low concentration source region, and

wherein a diffusion depth of the low concentration source region is equal to that of source/drain regions of the MOSFET.

2. The semiconductor device of claim 1 , wherein the peripheral circuit further includes a first conductivity type MOSFET.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2026
From: PANASONIC HOLDINGS CORPORATION
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 074237/0726 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2008
From: HARADA, YUJI; SAWADA, KAZUYUKI; NIWAYAMA, MASAHIKO; OKITA, MASAAKI
To: PANASONIC CORPORATION
Reel/Frame 021865/0673 →