IP Library Granted Patent US 8,106,479
Granted Patent B1
US 8,106,479 · App. 12/243,146 · Granted Jan 31, 2012

Patterned capacitor ground shield for inductor in an integrated circuit

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Quick Facts
Patent No.
US 8,106,479
App. No.
12/243,146
Granted
Jan 31, 2012
Kind
B1
Abstract

Integrated circuits are disclosed including at least one inductor-capacitor component, where each of the inductor-capacitor components includes an inductor and a capacitor constructed between the inductor and a substrate. The inductor includes at least one metal loop over a shield pattern forming a first capacitor terminal over patterned oxide layer with a second capacitor layer between the patterned oxide layer and the substrate.

Claims (17)

1. An integrated circuit, comprising at least one inductor-capacitor component further comprising an inductor, and a capacitor disposed between said inductor and a substrate,

wherein said inductor includes a first inductor terminal coupled through at least one metal loop to a second inductor terminal over a shield pattern layer, said shield pattern layer separated by an oxide pattern layer from said substrate, said shield pattern layer including a gate of a transistor; and

wherein said capacitor includes a first capacitor terminal as said shield pattern layer and a second capacitor layer disposed between said substrate and a boundary of at least one of said shield pattern layer and said oxide pattern layer.

2. The integrated circuit of claim 1 , wherein said shield pattern layer is composed of polysilicon.

3. The integrated circuit of claim 1 , wherein said oxide pattern layer is composed from a thin oxide layer belonging to a collection of oxide layers in said integrated circuit, including at least one oxide layer that is thicker than said thin oxide layer.

4. The integrated circuit of claim 3 , wherein said thin oxide layer is the thinnest of said oxide layers in said integrated circuit.

5. The integrated circuit of claim 1 , wherein said metal loop comprises at least one metal layer separated by at least one layer of inter-metal dielectric from said shield pattern layer.

6. The integrated circuit of claim 5 , wherein said metal loop further comprises at least two metal layers electrically coupled by at least one via.

7. The integrated circuit of claim 1 , wherein said integrated circuit is a CMOS integrated circuit.

8. The integrated circuit of claim 1 , wherein said integrated circuit is a gallium arsenide integrated circuit.

9. The integrated circuit of claim 1 , further comprising an RC filter comprising a resistor coupled to said capacitor.

10. The integrated circuit of claim 1 , wherein said inductor-capacitor component is configured as a parallel LC circuit

with said first inductor terminal electrically coupled to said first capacitor terminal and

with said second inductor terminal electrically coupled to said second capacitor layer.

11. The integrated circuit of claim 1 , wherein said inductor-capacitor component is configured as a series LC circuit

with a first terminal as said second inductor terminal and a second terminal as said second capacitor layer and

with said first inductor terminal electrically coupled to said first capacitor terminal.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2012
From: QUALCOMM ATHEROS, INC.
To: QUALCOMM INCORPORATED
Reel/Frame 029328/0052 →
MERGER Recorded Sep 16, 2011
From: ATHEROS COMMUNICATIONS, INC.
To: QUALCOMM ATHEROS, INC.
Reel/Frame 026919/0169 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2008
From: NATHAWAD, LALITKUMAR
To: ATHEROS COMMUNICATIONS, INC.
Reel/Frame 021615/0212 →