Associative list processing unit
View Patent ↗An associative list processing unit and method comprising employing a plurality of prioritized cell blocks and permitting inserts to occur in a single clock cycle if all of the cell blocks are not full. Also, an associative list processing unit and method comprising employing a plurality of prioritized cell blocks and using a tree of prioritized multiplexers descending from the plurality of cell blocks.
1. An associative list processing unit comprising:
a plurality of prioritized cell blocks; and
a tree of prioritized multiplexers descending from said plurality of cell blocks; and
wherein said tree adds a phantom cell having a logical lower priority than the lowest priority cells.
2. The associative list processing unit of claim 1 additionally comprising first-in first-out queues following each multiplexer.
3. The associative list processing unit of claim 1 wherein each multiplexer is an asynchronous, stateless circuit passing through the highest priority valid input.
4. The associative list processing unit of claim 1 operating in single-match mode.
5. The associative list processing unit of claim 1 operating in multiple-match mode.
6. An associative list processing method comprising the steps of:
employing a plurality of prioritized cell blocks;
using a tree of prioritized multiplexers descending from the plurality of cell blocks; and
adding into the tree a phantom cell having a logical lower priority than the lowest priority cells.
7. The associative list processing method of claim 6 additionally comprising employing first-in first-out queues following each multiplexer.
8. The associative list processing method of claim 6 wherein each multiplexer is an asynchronous, stateless circuit passing through the highest priority valid input.
9. The associative list processing method of claim 6 operating in single-match mode.
10. The associative list processing method of claim 6 operating in multiple-match mode.