Thin film transistor array panel and method for manufacturing the same
View Patent ↗The present invention relates to a thin film transistor array panel and a manufacturing method thereof. The thin film transistor array panel according to the present invention includes a substrate, a light blocking member formed on the substrate, a gate line disposed on the light blocking member. The gate line and the light blocking member define a closed region A color filter is formed in the closed region and contacts the side surface of the gate line. A gate insulating layer is formed on the gate line and the color filter, a data line and a drain electrode are formed on the gate insulating layer, and a pixel electrode is connected to the drain electrode.
1. A thin film transistor array panel comprising:
a substrate;
a light blocking member formed on the substrate;
a gate line disposed on the light blocking member;
a color filter having a portion contacting a side surface of the gate line;
a gate insulating layer formed on the gate line and on the color filter;
a data line and a drain electrode formed on the gate insulating layer; and
a pixel electrode connected to the drain electrode,
wherein the gate line has a substantially closed-loop shape that surrounds the color filter.
2. The thin film transistor array panel of claim 1 , wherein
a planar shape of the gate line is substantially the same as a planar shape of the light blocking member.
3. The thin film transistor array panel of claim 2 , wherein
the planar shape of the light blocking member is a ladder shape.
4. The thin film transistor array panel of claim 1 , wherein
the gate line comprises copper.
5. The thin film transistor array panel of claim 4 , wherein
the gate line comprises an upper layer and a lower layer, and the upper layer includes copper.
6. The thin film transistor array panel of claim 5 , wherein
the gate line further comprises a coating formed on a surface of the upper layer.
7. The thin film transistor array panel of claim 6 , wherein
the coating comprises CuF2 or CuFxOy.
8. The thin film transistor array panel of claim 5 , wherein
the lower layer comprises molybdenum or a molybdenum alloy.
9. The thin film transistor array panel of claim 1 , wherein
a sum of a thickness of the light blocking member and a thickness of the gate line is in a range of about 1 μm to about 4 μm.
10. The thin film transistor array panel of claim 5 , wherein
the thickness of the upper layer is in a range of about 0.3 μm to about 2 μm.
11. The thin film transistor array panel of claim 1 , wherein
a thickness of the color filter is equal to or less than the sum of a thickness of the light blocking member and a thickness of the gate line.
12. The thin film transistor array panel of claim 1 , wherein
the light blocking member comprises a metal or an organic material.
13. The thin film transistor array panel of claim 1 , wherein
the gate insulating layer comprises an organic material.
14. The thin film transistor array panel of claim 1 ,
wherein the gate line comprises a pair of stem lines and a plurality of branch lines, and
wherein the pair of stem lines and the plurality of branch lines together with the blocking member establish a barrier that defines a closed region.