Wireless clock regeneration and synchronization
View Patent ↗A method and apparatus are described for regenerating a local clock within a wireless module and synchronizing the local clock with a wireless host clock. For one embodiment, the wireless module generates a local clock, counts the cycles of the clock during a common timing reference period maintained wirelessly between the wireless module and the host, receives a count of the host clock during the same common timing reference period, and adjusts the local clock signal based upon a comparison of the two counts. For one embodiment, the wireless module further receives timing references from the host and, in addition, receives packets of audio samples from the host accompanied by a timestamp, the timestamp based upon the host timing reference, and outputs the audio sample at the time designated by the timestamp.
1. A method comprising:
generating a local clock within a wireless module;
counting a local clock count of the local clock during a common timing reference period that is common to the wireless module and a host and is maintained wirelessly between the wireless module and the host over a wireless link;
receiving, from the host over the wireless link, a host clock count of a host clock during the common timing reference period; and
adjusting the local clock based upon a comparison of the local clock count with the host clock count,
wherein the common timing reference period is maintained wirelessly by:
transmitting, from the host to the wireless module over the wireless link, a first control signal at a first predetermined interval;
transmitting, from the wireless module to the host over the wireless link, a second control signal at a second predetermined interval;
determining a difference in time between the transmitting of the first and second control signals; and
adjusting the first predetermined interval or the second predetermined interval to bring the first and second predetermined intervals within a predetermined time difference tolerance.
2. The method of claim 1 , further comprising:
receiving a wireless transmission from the host, wherein the wireless transmission includes audio samples and a timestamp based upon a host timing reference; and
outputting the audio sample at a time designated by the timestamp to a speaker.
3. The method of claim 2 , wherein the timestamp includes a clock count in reference to the host timing reference.
4. The method of claim 1 , wherein generating the local clock within the wireless module comprises:
receiving a host clock frequency from the host; and
generating a clock signal at the same frequency or derivative of the same frequency as the host clock frequency.
5. The method of claim 1 , wherein generating the local clock within the wireless module comprises:
receiving audio samples from the host;
deriving a host clock frequency from the audio samples; and
generating a clock signal at the same frequency or derivative of the same frequency as the host clock frequency.
6. The method of claim 1 , further comprising:
receiving, from the host over the wireless link, an initial host clock count during an initial period of the common timing reference period; and
initializing the local clock count to the initial host clock count.
7. A wireless module comprising:
a phase-locked loop (PLL) circuit to generate a local clock;
a radio to receive, from a host over a wireless link, a host clock count of a host clock during a common timing reference period that is common to and is maintained wirelessly between the wireless module and the host over the wireless link; and
a processing device coupled to the PLL and the radio, the processing device to count the local clock during the common timing reference period, and adjust the PLL based upon a comparison of the local clock count with the host clock count, wherein
the radio receives, from the host over the wireless link, a first control signal at a first predetermined interval, transmits to the host over the wireless link, a second control signal at a second predetermined interval, and
the processing device determines a difference in timing between the first and second control signals and adjusts the second predetermined interval to bring the first and second predetermined intervals within a predetermined time difference tolerance to maintain the common timing reference period.
8. The wireless module of claim 7 , wherein
the radio to further receive a wireless transmission from the host, wherein the transmission includes audio samples and a timestamp based upon a host timing reference; and
the processing device to further output the audio samples at a time designated by the timestamp to a speaker.
9. The wireless module of claim 8 , wherein the timestamp includes a clock count in reference to the host clock.
10. The wireless module of claim 7 , wherein generating a local clock comprises:
the radio receiving a host clock frequency from the host; and
the processing device adjusting the PLL to generate a clock signal at the same frequency or derivative of the same frequency as the host clock frequency.
11. The wireless module of claim 7 , wherein
the radio to further receive, from the host over the wireless link, an initial host clock count during an initial period of the common timing reference period; and
the processing device to initialize the local clock count to the initial host clock count.
12. The wireless module of claim 7 , further comprising:
a voltage controlled oscillator (VCO) coupled to the processing device and the PLL, wherein the VCO receives a control voltage from the processing device and outputs a corresponding frequency input to the PLL to adjust the local clock.
13. The wireless module of claim 12 , wherein the VCO is a voltage controlled crystal oscillator (VCXO).
14. A system comprising:
a host including
a host processing device to count a host clock;
a host radio to transmit the count of the host clock; and
a wireless module (WM) including
a phase-locked loop (PLL) circuit to generate a local clock,
a WM radio to receive, from the host over a wireless link, a count of a host clock count of the host clock during a common timing reference period that is common to and is maintained wirelessly between the WM and the host over the wireless link, and
a WM processing device coupled to the PLL and the WM radio, the WM processing device to
count a local clock count of the local clock during the common timing reference period, and
adjust the PLL based upon a comparison of the local clock count with the host clock count,
wherein the WM radio receives, from the host over the wireless link, a first control signal at a first predetermined interval, transmits to the host over the wireless link, a second control signal at a second predetermined interval; and
the WM processing device determines a difference in timing between the first and second control signals and adjusts the second predetermined interval to bring the first and second predetermined intervals within a predetermined time difference tolerance to maintain the common timing reference period.
15. The system of claim 14 , wherein
the WM radio to further receive a wireless transmission from the host, wherein the wireless transmission includes an audio sample and a timestamp based upon the common timing reference period; and
the processing device to output the audio sample at a time designated by the timestamp to a speaker.
16. The system of claim 15 , wherein the timestamp includes a clock count in reference to a host timing reference.
17. The system of claim 14 , wherein generating the local clock comprises:
the host radio transmitting a host clock frequency;
the WM radio receiving the host clock frequency; and
the WM processing device adjusting the PLL to generate a clock signal at the same frequency or derivative of the same frequency as the host clock frequency.
18. The system of claim 14 , wherein
the host radio to further transmit an initial host clock count during an initial period of the common timing reference period;
the WM radio to further receive the initial host clock count; and
the processing device to initialize the local clock count to the initial host clock count.
19. The system of claim 14 , wherein the WM further comprises:
a voltage controlled oscillator (VCO) coupled to the WM processing device and the PLL, wherein the VCO receives a control voltage from the WM processing device and outputs a corresponding frequency input to the PLL to adjust the local clock.
20. The wireless module of claim 19 , wherein the VCO is a voltage controlled crystal oscillator (VCXO).