Double broken seal ring
The amount of signal propagation and moisture penetration and corresponding reliability problems due to moisture penetration degradation in an IC can be reduced by fabricating two seal rings with non-adjacent gaps. In one embodiment, the same effect can be achieved by fabricating a wide seal ring with a channel having offset ingress and egress portions. Either of these embodiments can also have grounded seal ring segments which further reduce signal propagation.
1. A sealing system for an integrated circuit, comprising:
a first seal ring circumscribing the integrated circuit, the first seal ring including at least one gap;
a second seal ring circumscribing the first seal ring, the second seal ring including at least one gap offset from the at least one gap of the first seal ring; and
a doped area under each gap having a dopant concentration that is lower than a dopant concentration directly beneath any portion of the first and second seal rings, said doped areas, increasing resistivity to signal propagation across each gap.
2. The sealing system of claim 1 further comprising at least one grounded pad connected to the first seal ring.
3. The sealing system of claim 1 wherein the first seal ring comprises at least two gaps and the second seal ring comprises at least two gaps.
4. The sealing system of claim 1 further comprising at least one grounded pad connected to the second seal ring.
5. A sealing system for an integrated circuit (IC), comprising:
a first seal means circumscribing the integrated circuit, the first seal means including at least one gap;
a first doped channel having a first dopant concentration underlying and following a path of the first seal means; and
a second seal means circumscribing the first seal means, the second seal means including at least one gap offset from the at least one gap of the first seal means;
a second doped channel having a second dopant concentration underlying and following a path of the second seal means,
wherein at least one gap portion of the first doped channel underlies the at least one gap of the first seal means and has a dopant concentration less than the first dopant concentration.
6. The sealing system of claim 5 further comprising a grounding means connected to the first seal means.
7. The sealing system of claim 5 wherein the first seal means comprises at least two gaps and the second seal means comprises at least two gaps.
8. The sealing system of claim 5 further comprising a grounding means connected to the second seal means.
9. The sealing system of claim 8 , where the grounding means is grounded via a pin on the IC.
10. The sealing system of claim 5 wherein a gap portion of the second doped channel underlying the at least one gap of the second seal means has a dopant concentration less than the second dopant concentration.
11. The sealing system of claim 5 wherein the at least one gap portion of the first doped channel is substantially undoped.
12. An integrated circuit with a sealing system, comprising:
a substrate including a first doped channel having a first dopant concentration, the first doped channel including a gap portion having a dopant concentration less than the first dopant concentration;
a first seal ring circumscribing the integrated circuit overlying and following a path of the first doped channel, the first seal ring including at least one gap overlying the gap portion of the first doped channel; and
a second seal ring circumscribing the first seal ring.
13. The integrated circuit of claim 12 , wherein the at least one gap portion of the first doped channel is substantially undoped.
14. A method for forming a sealing system for an integrated circuit, comprising:
providing a substrate;
forming a first doped channel in the substrate having a first dopant concentration, the first doped channel including at least one gap portion having a dopant concentration less than the first dopant concentration;
forming a second doped channel in the substrate having a second dopant concentration, the second doped channel including at least one gap portion having a dopant concentration less than the second dopant concentration;
forming a first seal ring circumscribing the integrated circuit overlying and following the first doped channel, the first seal ring including at least one gap overlying the at least one gap portion of the first doped channel; and
forming a second seal ring circumscribing the first seal ring overlying and following the second doped channel, the second seal ring including at least one gap offset from the at least one gap of the first seal ring and overlying the at least one gap portion of the second doped channel.
15. The method of claim 14 including blocking a doping of the at least one gap portion of the first doped channel when forming the first doped channel and blocking a doping of the at least one gap portion of the second doped channel when forming the second doped channel.
16. A sealing system for an integrated circuit, comprising:
a substrate;
a first doped channel following a first path along the substrate, the first doped channel having a first dopant concentration and having at least one gap, a dopant concentration of the at least one gap being different than the first dopant concentration;
a first seal ring circumscribing the integrated circuit and overlying and following the first doped channel, the first seal ring including at least one gap overlying the at least one gap in the first doped channel;
a second doped channel following a second path along the substrate, circumscribing the first doped path, the second doped channel having a second dopant concentration and having at least one gap, a dopant concentration of the at least one gap of the second doped channel being different than the second dopant concentration;
a second seal ring circumscribing the first seal ring and overlying and following the second doped channel, the second seal ring including at least one gap offset from the at least one gap of the first seal ring and overlying the at least one gap in the second doped channel.
17. The sealing system of claim 16 , wherein the dopant concentration of the at least one gap in the first doped channel is substantially zero.
18. The sealing system of claim 16 , including at least one grounded pad connected to the second seal ring.
19. The sealing system of claim 16 , wherein the dopant concentration of the at least one gap of the first doped channel is less than the first dopant concentration.
20. A method for forming a sealing system for an integrated circuit, comprising:
steps for providing a substrate;
steps for forming a first doped channel in the substrate having a first dopant concentration, the first doped channel including at least one gap portion having a dopant concentration less than the first dopant concentration;
steps for forming a second doped channel in the substrate having a second dopant concentration, the second doped channel including at least one gap portion having a dopant concentration less than the second dopant concentration;
steps for forming a first seal ring circumscribing the integrated circuit overlying and following the first doped channel, the first seal ring including at least one gap overlying the at least one gap portion of the first doped channel; and
steps for forming a second seal ring circumscribing the first seal ring overlying and following the second doped channel, the second seal ring including at least one gap offset from the at least one gap of the first seal ring and overlying the at least one gap portion of the second doped channel.