Mesosynchronous data bus apparatus and method of data transmission
View Patent ↗A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.
1. An interconnection system, comprising:
a first node;
a second node in communication with the first node, wherein the first and the second node communicate over a bus;
a first clock, the clock being provided to the first node and the second node; and
a second clock, having a first integral relationship to the first clock,
wherein a character comprised of bits is transmitted between the first node and the second node serially at a clock rate having a second integral relationship to the first clock, the second clock having a time delay with respect to the first clock such that the transmission time of bits between an output of the first node and an output of the second node is maintained substantially constant.
2. The system of claim 1 , wherein the first and the second integral relationship are the same integral relationship.
3. The system of claim 1 , wherein a received character is converted from a serial data format to a plurality of streams of data having a serial data format at a lower clock speed than that of the second clock.
4. The system of claim 3 , wherein the time delay of the second clock is adjusted so that a same bit location of a subsequently received character is converted to a same relative bit location in the serial data streams.
5. The system of claim 3 , wherein each of the plurality of serial data streams is routed to one of a memory or another node.
6. The system of claim 5 , wherein the routing is determined by a received character.
7. The system of claim 5 , wherein when the character is routed to another node, and the data is re-serialized using the second clock.
8. The system of claim 7 , wherein the re-serialized data is transmitted on one of a plurality of lines connecting two nodes.
9. The system of claim 8 , wherein the re-serialized data is bound to a selected one of the plurality of lines.
10. The system of claim 1 , wherein the time delay of a lane is adjusted so that the overall time delay of the lane, when measured between the output of the first node and the output of the second node, is substantially constant.
11. The system of claim 10 , wherein a received character on one of a plurality of lanes of is converted from a first serial data format to a plurality of second serial data streams independently of a received character on another of the plurality of lanes.
12. The system of claim 11 , wherein the number of second serial data packets is equal to the number of bits in the character.
13. A node of an interconnection system, comprising:
a data receiving circuit;
a data transmitting circuit;
a switch connecting the data receiving and the data transmitting circuit;
a circuit operable to maintain a sampling time in a fixed relationship to a first bit of a character of a received character having a plurality of bits; and
an input data buffer configured to resample the first bit so that an overall time delay measured between the resampled bit and a corresponding resampled bit at another module is maintained substantially constant.
14. The node of claim 13 , wherein the circuit is a data clock recovery circuit.
15. The node of claim 13 , wherein the input data buffer operates at a clock frequency that is an integral submultiple of a data clock rate.
16. The node of claim 13 , wherein the switch is operable to route the received character to at least one of another node or a memory.
17. The node of claim 13 , wherein the switch output is transmitted at a data clock rate.
18. The node of claim 13 , wherein the input data buffer is operable to deserialize the received character into a plurality of data packets, and an output data buffer is operable to reserialize the switch output data into a character.
19. The node of claim 13 , wherein the character is received on a first line of a plurality of lines of a first port, and the character is transmitted to another node on a selectable one of a plurality of lines of a second port.
20. A method of managing an interconnection system, the system comprising a plurality of nodes in communication with each other; the method comprising:
transmitting a character of data comprising a plurality of bits from a first node to a second node;
receiving the character at a second node;
recovering a clock from the received data and aligning a sampling time of the character; and
re-sampling the sampled data at a submultiple of the clock frequency and adjusting the phase or time delay of the re-sampling clock so that the overall time delay between the transmitted character from the first node and a character on the same lane transmitted by the second node is substantially constant.