IP Library Granted Patent US 8,787,774
Granted Patent B2
US 8,787,774 · App. 12/245,867 · Granted Jul 22, 2014

Method and system for a narrowband, non-linear optoelectronic receiver

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Quick Facts
Patent No.
US 8,787,774
App. No.
12/245,867
Granted
Jul 22, 2014
Kind
B2
Abstract

Methods and systems for a narrowband, non-linear optoelectronic receiver are disclosed and may include amplifying a received signal, limiting a bandwidth of the received signal, and restoring the signal utilizing a level restorer, which may include a non-return to zero (NRZ) level restorer. The NRZ level restorer may include a pulse-triggered bistable circuit, which may include two parallel inverters, with one being a feedback path for the other. The inverters may be single-ended or differential. A photogenerated signal may be amplified in the receiver utilizing a transimpedance amplifier and programmable gain amplifiers (PGAs). A received electrical signal may be amplified via PGAs. The bandwidth of the received signal may be limited utilizing one or more of: a low pass filter, a bandpass filter, a high pass filter, a differentiator, or a series capacitance on the chip. The signal may be received from a photodiode integrated on the chip.

Claims (21)

1. A method for processing signals, the method comprising:

in a receiver on a chip,

amplifying a received signal that is generated from a received optical signal;

limiting a bandwidth of said received signal utilizing a band pass filter that results in a narrow frequency band comprising a maximum data tone of the received signal; and

restoring said received signal utilizing a non-return to zero (NRZ) level restorer comprising a pulse-triggered bistable circuit, wherein said pulse-triggered bistable circuit comprises two parallel inverters, and wherein a first of said inverters comprises a feedback path for a second of said inverters.

2. The method according to claim 1 , wherein said inverters comprise single-ended inverters.

3. The method according to claim 1 , wherein said inverters comprise differential inverters.

4. The method according to claim 1 , comprising amplifying a photogenerated signal in said receiver utilizing a transimpedance amplifier and one or more variable gain amplifiers (VGAs).

5. The method according to claim 1 , comprising amplifying a received electrical signal via one or more VGAs.

6. The method according to claim 1 , comprising limiting said bandwidth of said received signal utilizing one or more of: a differentiator or a series capacitance on said chip.

7. The method according to claim 1 , comprising receiving said signal from a photodiode integrated on said chip.

8. A system for processing signals, the system comprising:

in a receiver on a chip, one or more circuits operable to amplify a received signal that is generated from a received optical signal;

said one or more circuits comprise a band pass filter that limits a bandwidth of said received signal to a narrow frequency band that comprises a maximum data tone of the received signal; and

said one or more circuits restore said received signal utilizing a Non-return to Zero (NRZ) level restorer comprising a pulse-triggered bistable circuit, wherein said pulse-triggered bistable circuit comprises two parallel inverters, and wherein a first of said inverters comprises a feedback path for a second of said inverters.

9. The system according to claim 8 , wherein said inverters comprise single-ended inverters.

10. The system according to claim 8 , wherein said inverters comprise differential inverters.

11. The system according to claim 8 , wherein said one or more circuits are enabled to amplify a photogenerated signal in said receiver utilizing a transimpedance amplifier and one or more variable gain amplifiers (VGAs).

12. The system according to claim 8 , wherein said one or more circuits are enabled to amplify a received electrical signal via one or more VGAs.

13. The system according to claim 8 , wherein said one or more circuits are enabled to limit said bandwidth of said received signal utilizing one or more of: a differentiator or a series capacitance on said chip.

14. The system according to claim 8 , wherein said one or more circuits are enabled to receive said signal from a photodiode integrated on said chip.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 058979 FRAME: 0027. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 24, 2022
From: LUXTERA LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 059496/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 058979/0027 →
RELEASE OF SECURITY INTEREST Recorded Dec 24, 2020
From: SILICON VALLEY BANK
To: LUXTERA, LLC
Reel/Frame 054855/0838 →
CHANGE OF NAME Recorded Feb 6, 2020
From: LUXTERA, INC.
To: LUXTERA LLC
Reel/Frame 052019/0811 →
SECURITY INTEREST Recorded Mar 29, 2017
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 042109/0140 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2012
From: GUCKENBERGER, JOHN ANDREW
To: LUXTERA INC.
Reel/Frame 028026/0351 →
SECURITY AGREEMENT Recorded Mar 17, 2010
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 024091/0191 →