Successive approximation ADC with binary error tolerance mechanism
View Patent ↗A successive approximation ADC is disclosed. A comparator receives and compares a sampled input signal and an output of a DAC. Non-binary successive approximation register (SAR) control logic controls sampling of the input signal and controls a sequence of comparisons based on comparison result of the comparator. The SAR control logic controls each comparison when signal or charge in the DAC has not been completely settled. A binary-error-tolerant corrector is then used to compensate the sampling error.
1. A successive approximation analog-to-digital converter (ADC), comprising:
a digital-to-analog converter (DAC);
a comparator that receives a sampled input signal at one input node, and receives an output of the DAC at another input node;
non-binary successive approximation register (SAR) control logic that controls sampling of the input signal and controls a sequence of comparisons based on a comparison result of the comparator, wherein the SAR control logic controls each comparison when signal or charge in the DAC has not been completely settled; and
a corrector that compensates error incurred in the output of the comparator.
2. The ADC of claim 1 , wherein the SAR control logic controls each comparison when signal or charge in the DAC becomes stable to an accuracy of at least one bit.
3. The ADC of claim 2 , wherein the SAR control logic controls each comparison when signal or charge in the DAC becomes stable to an accuracy of x bits.
4. The ADC of claim 3 , wherein the DAC comprises an array of capacitors with binary weighted values, and at least one compensating capacitor inserted among the capacitors with binary weighted values.
5. The ADC of claim 4 , wherein the DAC requires compensating capacitors with amount of [(n−2)/x] for an n-bit ADC, where [ ] is the Gaussian operator that takes integer portion of a value.
6. The ADC of claim 5 , wherein the corrector comprises a plurality of adders that respectively add up corresponding output bits of the comparator.
7. The ADC of claim 1 , wherein the ADC has n bits of resolution.
8. The ADC of claim 7 , wherein the SAR control logic controls each comparison when signal or charge in the DAC becomes stable to an accuracy of x bits, and the DAC requires compensating capacitors with amount of [(n−2)/x] for the n-bit ADC, where [ ] is the Gaussian operator that takes an integer portion of a value.
9. The DAC of claim 8 , wherein the ADC has eight (8) bits of resolution, and the DAC includes an array of capacitors with non-binary weighted value as follows:
C7=2C6=4C5=4C5c=8C4=16C3=16C3c=32C2=64C1=64C1c.
10. The ADC of claim 9 , wherein the output of SAR control logic is corrected by the corrector according to a correction operation as follows:
Output=−21+128 . B 1+64 . B 2+32 . B 3+32 . B 4+16 . B 5+8 . B 6+8 . B 7+4 . B 8+2 . B 9+2 . B 10+1 . B 11.
11. The ADC of claim 10 , wherein the corrector comprises a plurality of adders for respectively adding up corresponding bits with a same weighting value in said correction operation.
12. The ADC of claim 11 , wherein the correction operation is performed to transform (B 1 B 2 B 3 . . . B 11 ) to (A 1 A 2 A 3 . . . A 8 ) as follows:
1
1
1
0
1
0
1
1
B
1
B
2
B
3
B
5
B
6
B
8
B
9
B
11
+
B
4
B
7
B
10
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
.