IP Library Granted Patent US 8,315,678
Granted Patent B2
US 8,315,678 · App. 12/247,475 · Granted Nov 20, 2012

Systems, methods, and apparatus for multilayer superconducting printed circuit boards

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Quick Facts
Patent No.
US 8,315,678
App. No.
12/247,475
Granted
Nov 20, 2012
Kind
B2
Abstract

Superconducting connections are provided to internal layers of a multi-layer circuit board structure, for example by superconducting vias.

Claims (33)

1. A multilayer superconducting printed circuit board, comprising:

a first electrically insulative substrate layer having a first surface and a second surface opposed to the first surface, wherein the first electrically insulative substrate layer has at least a first hole that extends from the first surface to the second surface and wherein at least a portion of an inner surface of the first hole is coated with a binder material;

at least a second electrically insulative substrate layer having a first surface and a second surface opposed to the first surface, the second electrically insulative substrate layer physically coupled to the first electrically insulative substrate layer;

a first superconducting current path consisting of an elemental or alloyed superconducting metal positioned on a first surface side of the first electrically insulative substrate layer;

a second superconducting current path consisting of an elemental or alloyed superconducting metal positioned between the first and the second electrically insulative substrate layers; and

a third superconducting current path that extends through the first hole in the first electrically insulative substrate layer and superconductingly couples the first superconducting current path with the second superconducting current path, wherein the third superconducting current path consists of an elemental or alloyed superconducting metal plated on at least a portion of the binder material on the inner surface of the first hole.

2. The superconducting printed circuit board of claim 1 wherein the first superconducting current path is carried on the first surface of the first insulative substrate layer.

3. The superconducting printed circuit board of claim 2 wherein the first surface of the first insulative substrate layer is a first outer surface physically accessible from an exterior of the superconducting printed circuit board.

4. The superconducting printed circuit board of claim 3 wherein the second superconducting current path is carried on the second surface of the first insulative substrate layer.

5. The superconducting printed circuit board of claim 3 wherein the second superconducting current path is carried on the first surface of the second insulative substrate layer and the first surface of the second insulative substrate layer is successively adjacent the second surface of the first insulative substrate layer.

6. The superconducting printed circuit board of claim 1 , further comprising:

a fourth superconducting current path positioned to be on a second surface side of the second electrically insulative substrate layer; and

a fifth superconducting current path that extends through the second electrically insulative substrate layer and superconductingly couples the fourth superconducting current path with at least one of the first and the second superconducting current paths.

7. The superconducting printed circuit board of claim 6 wherein the first surface of the first insulative substrate layer is a first outer surface physically accessible from an exterior of the superconducting printed circuit board and the second surface of the second electrically insulative substrate layer is a second outer surface physically accessible from the exterior of the superconducting printed circuit board.

8. The superconducting printed circuit board of claim 6 , further comprising:

at least a third electrically insulative substrate layer having a first surface and a second surface opposed to the first surface, the third electrically insulative substrate layer physically coupled to the second electrically insulative substrate layer;

at least one additional superconducting current path carried by the second surface of the third electrically insulative substrate layer; and

a sixth superconducting current path that extends through the third electrically insulative substrate layer and superconductingly couples at least the one additional superconducting current path with at least one of the first, the second, and the fourth superconducting current paths.

9. The superconducting printed circuit board of claim 8 wherein the second electrically insulative substrate layer is sandwiched between the first and the third electrically insulative substrate layers.

10. The superconducting printed circuit board of claim 1 wherein at least one of the first superconducting current path and the second current path is plated on a non-superconducting trace.

11. The superconducting printed circuit board of claim 1 wherein the binder material comprises palladium.

12. The superconducting printed circuit board of claim 1 , further comprising a distinct plug inside the first hole.

13. The superconducting printed circuit board of claim 12 wherein the distinct plug includes a piece of wire secured in place by a solder connection.

14. The superconducting printed circuit board of claim 1 wherein at least one of the first, the second and the third superconducting current paths comprises tin.

15. The superconducting printed circuit board of claim 1 wherein at least one of the first, the second and the third superconducting current path comprises niobium.

16. A method of fabricating a superconducting via in a multilayer superconducting printed circuit board comprising a first electrically insulative substrate layer having a first surface and a second surface opposed to the first surface; at least a second electrically insulative substrate layer having a first surface and a second surface opposed to the first surface, the second electrically insulative substrate layer physically coupled to the first electrically insulative substrate layer; a first superconducting current path consisting of an elemental or alloyed superconducting metal positioned on a first surface side of the first electrically insulative substrate layer; and a second superconducting current path consisting of an elemental or alloyed superconducting metal positioned between the first and the second electrically insulative substrate layers; the method comprising:

forming a hole through at least a portion of the first electrically insulative substrate layer;

coating at least a portion of an inner surface of the hole with a binding material; and

plating at least a portion of the inner surface of the hole with an elemental or alloyed superconducting metal, wherein the binding material binds the superconducting metal to at least a portion of the inner surface of the hole such that a third superconducting current path extends through the hole and superconductingly couples the first superconducting current path with the second superconducting current path.

17. The method of claim 16 wherein the binding material comprises palladium.

18. The method of claim 16 wherein the superconducting metal comprises tin.

19. The method of claim 16 wherein the superconducting metal comprises niobium.

20. The method of claim 16 wherein forming a hole through at least a portion of the first electrically insulative substrate layer includes drilling the hole.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2025
From: PSPIB UNITAS INVESTMENTS II INC.
To: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
Reel/Frame 070470/0098 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 14, 2023
From: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
To: PSPIB UNITAS INVESTMENTS II INC., AS COLLATERAL AGENT
Reel/Frame 063340/0888 →
RELEASE OF SECURITY INTEREST Recorded Sep 20, 2022
From: PSPIB UNITAS INVESTMENTS II INC., IN ITS CAPACITY AS COLLATERAL AGENT
To: D-WAVE SYSTEMS INC.
Reel/Frame 061493/0694 →
SECURITY INTEREST Recorded Mar 3, 2022
From: D-WAVE SYSTEMS INC.
To: PSPIB UNITAS INVESTMENTS II INC.
Reel/Frame 059317/0871 →
SECURITY INTEREST Recorded Nov 29, 2019
From: D-WAVE SYSTEMS INC.
To: BDC CAPITAL INC.
Reel/Frame 051144/0499 →
SECURITY INTEREST Recorded Mar 22, 2019
From: D-WAVE SYSTEMS INC.
To: BDC CAPITAL INC.
Reel/Frame 048674/0188 →
RELEASE OF SECURITY INTEREST Recorded Apr 13, 2017
From: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 042252/0256 →
CORRECTIVE ASSIGNMENT TO REMOVE APPL. NO. 8733763 PREVIOUSLY RECORDED AT REEL: 034841 FRAME: 0497. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Jan 30, 2015
From: D-WAVE SYSTEMS INC.
To: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
Reel/Frame 034862/0237 →
SECURITY INTEREST Recorded Jan 29, 2015
From: D-WAVE SYSTEMS INC.
To: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
Reel/Frame 034841/0497 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2008
From: UCHAYKIN, SERGEY V.
To: D-WAVE SYSTEMS INC.
Reel/Frame 021963/0525 →