Through substrate via process
A through substrate via (TSV) process is provided. A substrate having a first side and a second side opposite the first side is provided. A plurality of holes is formed in the substrate at the first side. A first dielectric layer is formed on a sidewall and a bottom of the holes. A second dielectric layer is formed in the holes, wherein a material of the second dielectric layer is different from that of the first dielectric layer. A semiconductor device and an interconnect are formed on the substrate at the first side. At least a portion of the substrate at the second side is removed to expose the second dielectric layer in the holes. The second dielectric layer is removed. A conductive layer is formed in the holes.
1. A through substrate via (TSV) process, comprising:
providing a substrate, comprising a first side and a second side opposite to the first side;
forming a plurality of holes in the substrate at the first side;
forming a first dielectric layer on a sidewall and a bottom of the holes;
forming a second dielectric layer in the holes, wherein a material of the second dielectric layer is different from a material of the first dielectric layer;
forming a semiconductor device, a plurality of dielectric layers and an interconnect on the substrate at the first side, wherein the dielectric layers in which the interconnect are formed cover the semiconductor device;
removing at least a portion of the substrate at the second side, so as to expose the second dielectric layer in the holes;
removing the second dielectric layer;
forming a conductive layer in the holes, wherein the dielectric layers and the interconnect are formed on the conductive layer and the substrate; and
after forming the conductive layer in the holes, bonding the substrate to another substrate in a stacked manner,
wherein the step of forming the semiconductor device, the dielectric layers and the interconnect on the substrate at the first side is performed before the step of removing at least the portion of the substrate at the second side, but after the step of forming the second dielectric layer in the holes.
2. The TSV process according to claim 1 , wherein the first dielectric layer comprises silicon oxide or silicon nitride.
3. The TSV process according to claim 1 , wherein the second dielectric layer comprises silicon oxide or silicon nitride.
4. The TSV process according to claim 1 , wherein the step of forming the first dielectric layer comprises performing chemical vapor deposition (CVD).
5. The TSV process according to claim 1 , wherein the conductive layer comprises copper.
6. The TSV process according to claim 1 , wherein the step of removing a portion of the substrate at the second side comprises performing chemical mechanical polishing (CMP).
7. The TSV process according to claim 1 , wherein the step of removing the second dielectric layer comprises performing wet etching.
8. The TSV process according to claim 1 , wherein the step of forming the second dielectric layer comprises performing CVD.
9. The TSV process according to claim 1 , wherein the step of forming the conductive layer comprises:
forming a conductive material layer on the substrate at the second side, wherein the conductive material layer fills the holes; and
removing the conductive material layer outside the holes.
10. The TSV process according to claim 1 , wherein the semiconductor device comprises a metal oxide semiconductor (MOS) transistor.
11. The TSV process according to claim 1 , wherein the substrate comprises silicon.