IP Library Granted Patent US 7,795,973
Granted Patent B2
US 7,795,973 · App. 12/250,450 · Granted Sep 14, 2010

Programmable gain amplifier

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Quick Facts
Patent No.
US 7,795,973
App. No.
12/250,450
Granted
Sep 14, 2010
Kind
B2
Abstract

A programmable gain amplifier comprising alternatively selectable parallel circuits in a front end and independently selectable serial amplification circuits in a back end. The front end may include, for example, a plurality of transconductors in parallel and each configured to generate a current proportional to a received voltage. A ratio of the generated current to the received voltage being different for each of the transconductors. The back end is configured to receive an output of a selected member of the parallel circuits and may include a plurality of current or voltage mode amplifiers in series. For example, the back end may include a plurality of current-mode gain stages and switches configured to control which of the current-mode gain stages are used to amplify the output of the front end. The programmable gain amplifier may be used between a signal receiver and an analog to digital converter.

Claims (40)

1. A system comprising:

a front end comprising

a first transconductor configured to receive a voltage and generate a current proportional to the voltage received by the first transconductor,

a second transconductor in parallel with the first transconductor and configured to receive a voltage and generate a current proportional to the voltage received by the second transconductor, and

a switch configured to create a signal path from an input of the front end to an output of the front end through alternatively the first transconductor or the second transconductor; and

a back end comprising

a first current-mode gain stage configured to receive current from the front end and to generate a current proportional to the current received from the front end,

a second current-mode gain stage in series with the first current-mode gain stage, configured to receive current via the first current-mode gain stage, and configured to generate current proportional to the current received by the second current-mode gain stage, and

a switch configured to select whether or not the second current-mode gain stage is included in a signal path from an input of the back end to an output of the back end.

2. The system of claim 1 , wherein the front end is configured to operate in a differential mode.

3. The system of claim 1 , wherein the front end comprises at least three transconductors.

4. The system of claim 1 , wherein the switch of the front end is disposed between the first transconductor and the output of the front end.

5. The system of claim 1 , wherein the current generated by the second transconductor is at least 10 dB greater than the current generated by the first transconductor, in response to receiving a first voltage.

6. The system of claim 1 , wherein

a difference in dB between a current generated by the first transconductor and a current generated by the second transconductor, in response to receiving a first voltage, is greater than a gain in dB of the first current-mode gain stage.

7. The system of claim 1 , wherein the front end is configured to select gross steps in amplification and the back end is configured to select fine steps in amplification.

8. The system of claim 7 , wherein a total of the fine steps is greater than one of the gross steps.

9. The system of claim 1 , wherein the first transconductor is configured to operate in differential mode and at least one of the first and second current-mode gain stages is configured to operate in a single-ended mode.

10. The system of claim 1 , wherein the first current-mode gain stage is configured to amplify current by a different amount than the second current-mode gain stage.

11. The system of claim 1 , wherein the back end comprises at least three current-mode gain stages.

12. The system of claim 1 , wherein the back end further comprises a final current-mode gain stage configured to generate an output configured to match an input of an analog to digital converter.

13. The system of claim 1 , wherein the back end further comprises a circuit configured to convert a current output of a final current-mode gain stage to a voltage.

14. The system of claim 1 , wherein the first current-mode gain stage is configured to operate in a differential mode and the second current-mode gain stage is configured to operate in a single-ended mode.

15. The system of claim 1 , further comprising control logic configured to change the switch of the front end and the switch of the back end responsive to a magnitude of a signal received at the input of the front end.

16. The system of claim 1 , further comprising an analog to digital converter configured to receive the output of the back end and convert the output to a digital value.

17. The system of claim 1 , further comprising a signal source configured to provide a signal to the front end.

18. A method comprising:

receiving a signal;

setting a first switch to alternatively

create a first signal path through a first but not a second of a plurality of parallel transconductors, or

create the first signal path through the second but not the first of the plurality of parallel transconductors;

generating a first current proportional to a voltage of the signal by passing the signal through the first signal path;

setting a second switch to alternatively

create a second signal path through a first and a second of a plurality of serial current-mode gain stages, or

create the second signal path through the second but not the first of the serial current-mode gain stages; and

generating a second current proportional to the first current by passing the signal through the second signal path.

19. The method of claim 18 , further comprising determining a magnitude of a signal and selecting a setting for the first switch and a setting for the second switch such that the signal is amplified an amount responsive to the determined magnitude.

20. The method of claim 19 , wherein the preferred amount of amplification results in the signal optimized for an input voltage range of an analog to digital converter.

21. The method of claim 18 , further comprising converting the second current to a voltage.

22. The method of claim 18 , further comprising generating a digital value responsive to the second current using an analog to digital converter.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2018
From: BROADCOM EUROPE LIMITED
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 046019/0030 →
BUSINESS TRANSFER Recorded Nov 13, 2012
From: BROADCOM NETWORKS (EDINBURGH) LIMITED
To: BROADCOM EUROPE LIMITED
Reel/Frame 029291/0765 →
CHANGE OF NAME Recorded Nov 13, 2012
From: GIGLE NETWORKS LIMITED
To: BROADCOM NETWORKS (EDINBURGH) LIMITED
Reel/Frame 029289/0814 →
DISAVOWMENT OF PURPORTED PATENT RIGHTS ASSIGNMENT Recorded Dec 15, 2011
From: BROADCOM CORPORATION
To: GIGLE NETWORKS LIMITED
Reel/Frame 027390/0878 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2011
From: GIGLE NETWORKS LIMITED
To: BROADCOM CORPORATION
Reel/Frame 026404/0760 →
CHANGE OF NAME Recorded Jan 6, 2010
From: GIGLE SEMICONDUCTOR LIMITED
To: GIGLE NETWORKS LIMITED
Reel/Frame 023744/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2008
From: HURWITZ, JONATHAN EPHRIAM DAVID; BOFILL-PETIT, ADRIA; HENDERSON, ROBERT K.
To: GIGLE SEMICONDUCTOR LTD.
Reel/Frame 021675/0747 →