ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.
1 - 74 . (canceled)
75 . An adaptive computing engine, comprising:
a configurable logic unit including a plurality of heterogeneous computational elements and a logic unit interconnection network coupling the plurality of heterogeneous computational elements to each other, the plurality of heterogeneous computational elements including a first type of heterogeneous computational element performing a first operation and a second type of heterogeneous computational element performing a second, different operation;
a digital signal processing unit including a plurality of heterogeneous computational elements dedicated to digital signal processing, the digital signal processing unit configurable to perform a digital signal processing function; and
wherein configurable logic unit is configurable to perform a function via changing interconnections of the logic unit interconnection network between the plurality of heterogeneous computational elements.
76 . The computing engine of claim 75 , wherein the first and second types are different ones of a group of an adder, a multiplier, a register, and a function generator having data inputs and a control input to select a specific function.
77 . The computing engine claim 75 , further comprising an interconnection network coupled to the configurable logic unit and the digital signal processing unit, the interconnection network sending configuration information to the logic unit interconnection network.
78 . The computing engine of claim 75 , wherein the logic unit interconnection network includes multiplexers coupled to the two types of computational elements, the multiplexers routing data between the computational elements.
79 . The computing engine of claim 77 , wherein the logic unit interconnection network has denser interconnections than the interconnections of the interconnection network.
80 . The computing engine of claim 78 wherein the logic unit interconnection network routes control signals to control the multiplexers to switch data to the computational elements.
81 . The computing engine of claim 78 , wherein the configurable logic unit further includes a third type of computational element performing a third operation selected from the group of an adder, a multiplier, a register, and a function generator having data inputs and a control input to select a specific function.
82 . The computing engine of claim 75 , wherein the function is a logic function, arithmetic function or a register function.
83 . The computing engine of claim 75 , wherein the logic unit interconnection network provides second configuration information to configure the configurable logic unit to perform a second function.
84 . The computing engine of claim 75 , wherein the heterogeneous computational elements of the digital signal processing unit each perform a function selected from the group of multiplication, addition, subtraction, accumulation, summation and dynamic shift.
85 . The computing engine of claim 84 , wherein the digital signal processing unit includes a digital signal processing interconnection network coupling the computational elements to each other, the configuration information allowing the digital signal processing interconnection network to connect the computational elements to allow the digital signal processing unit to perform a second function.
86 . The computing engine of claim 85 , wherein the second function is one of fixed point arithmetic function, floating point arithmetic functions, filters, transformation functions.
87 . An adaptive computing engine, comprising:
a configurable logic unit including a plurality of computational elements;
a configurable signal processing unit including a signal processing interconnection network, and a plurality of heterogeneous computational elements including a multiplier computational element and an adder computational element, the signal processing interconnection network coupled to each of the heterogeneous computational elements; and
wherein the configurable signal processing unit is configured to perform a signal processing function via switching interconnections of the interconnection network between the plurality of heterogeneous computational elements.
88 . The computing engine of claim 87 , further comprising an interconnection network coupled to the configurable logic unit and the signal processing unit, the interconnection network sending configuration information to the configurable signal processing unit.
89 . The computing engine of claim 87 , wherein the plurality of computational elements of the configurable logic unit may include an adder, a register, or a function generator having data inputs and a control input to select a specific function.
90 . The computing engine of claim 87 , wherein the signal processing interconnection network includes multiplexers coupled to the multiplier and adder computational elements, the multiplexers routing data between the computational elements.
91 . The computing engine of claim 88 , wherein the signal processing interconnection network switches the interconnections between the heterogeneous computational elements to configure the signal processing unit to perform a second function.
92 . The computing engine of claim 91 , wherein the second function is one of fixed point arithmetic function, floating point arithmetic functions, filters, transformation functions.
93 . The computing engine of claim 87 , wherein the heterogeneous computational elements of the signal processing unit each perform a function from the group of subtraction, accumulation, summation and dynamic shift.
94 . An adaptive computing engine, comprising:
a configurable logic unit including a first plurality of heterogeneous computational elements and a logic unit interconnection network coupling the plurality of heterogeneous computational elements to each other, the plurality of heterogeneous computational elements including a first type of heterogeneous computational element performing a first operation and a second type of heterogeneous computational element performing a second, different operation; and
a configurable signal processing unit including a signal processing interconnection network, and a second plurality of heterogeneous computational elements logic unit, the signal processing interconnection network coupled to each of the heterogeneous computational elements.