Method to create super secondary grain growth in narrow trenches
View Patent ↗The present invention relates to a method for obtaining enlarged Cu grains in small trenches. More specifically it related to a method for creating enlarged copper grains or inducing super secondary grain growth in electrochemically deposited copper in narrow trenches and/or vias to be used in semiconductor devices.
1. A semiconductor device comprising at least one structure selected from the group consisting of a trench and a via, wherein the structure is filled with recrystallized electrochemically deposited copper, wherein at least 80% of said recrystallized electrochemically deposited copper consists of copper grains having a [100] orientation and dimensions of at least 10 microns.
2. The semiconductor device of claim 1 , wherein at least 93% of said recrystallized electrochemically deposited copper consists of said copper grains having a [100] orientation and dimensions of at least 10 microns.
3. The semiconductor device of claim 1 , wherein at least 98% of said recrystallized electrochemically deposited copper consist of said copper grains having a [100] orientation and dimensions of at least 10 micron.
4. The semiconductor device of claim 1 , wherein said copper grains with a [100] orientation have dimensions of at least 25 micrometers.
5. The semiconductor device of claim 1 , wherein said copper grains with a [100] orientation have dimensions of at least 100 micrometers.
6. The semiconductor device of claim 1 , wherein said structure is a trench, and wherein said trench has a width of from 50 nm to 200 nm.
7. The semiconductor device of claim 1 , wherein said structure is a trench, and wherein said trench has a width of less than 200 nm.
8. The semiconductor device of claim 7 , wherein said trench has an aspect ratio or a height to width ratio higher than 1.
9. The semiconductor device of claim 1 , wherein said recrystallized electrochemically deposited copper is laid upon a diffusion barrier layer.
10. The semiconductor device of claim 9 , wherein said diffusion barrier layer has a thickness of less than 8 nm.
11. The semiconductor device of claim 9 , wherein said diffusion barrier layer is a layer comprising a metal selected from the group consisting of tantalum, titanium, ruthenium, tungsten, manganese, and combinations thereof.
12. The semiconductor device of claim 9 , wherein said diffusion barrier layer comprises a material selected from the group consisting of α-tantalum, β-tantalum, tantalum nitride, and combinations thereof.
13. The semiconductor device of claim 9 , further comprising a copper seedlayer atop said diffusion barrier layer.
14. The semiconductor device of claim 13 , wherein said copper seedlayer is a manganese-containing seedlayer.
15. The semiconductor device of claim 14 , wherein said diffusion barrier layer comprises manganese.
16. The semiconductor device of claim 1 , having a surface that has been subjected to chemical mechanical polishing.
17. The semiconductor device of claim 1 , wherein the structure is a via.