Interconnect for surfing circuits
An interconnect for surfing circuits is presented. The interconnect includes at least one control signal line, at least one data signal line, and at least one variable capacitor coupled to the at least one control signal line and the at least one data signal line, wherein the capacitance of the variable capacitor is configured to be controlled by a control signal on the control signal line so that a velocity of a data signal transmitted on the at least one data signal line is determined by the value of the capacitance of the variable capacitor.
1. An interconnect, comprising:
at least one control signal line;
at least one data signal line; and
at least one variable capacitor coupled to the at least one control signal line and the at least one data signal line, wherein the capacitance of the variable capacitor is configured to be controlled by a control signal on the control signal line so that a velocity of a data signal transmitted on the at least one data signal line is determined by the value of the capacitance of the variable capacitor, wherein the control signal comprises a clock signal.
2. The interconnect of claim 1 , wherein the interconnect is a transmission line.
3. The interconnect of claim 2 , wherein the transmission line is operating in an inductance-capacitance (LC) mode.
4. The interconnect of claim 1 , wherein the variable capacitor is configured to provide energy gain on the data signal when the clock signal changes.
5. The interconnect of claim 1 , including at least one negative conductance device configured to restore a signal level of a signal transmitted on the at least one data signal line.
6. The interconnect of claim 5 , wherein the at least one negative conductance device is a sense amplifier.
7. The interconnect of claim 5 , wherein the at least one negative conductance device is at least one pair of cross-coupled inverters.
8. The interconnect of claim 1 , wherein the variable capacitor is a varactor.
9. The interconnect of claim 8 , wherein the varactor is a metal-oxide semiconductor (MOS) transistor.
10. The interconnect of claim 8 , wherein the varactor is a PN-junction varactor.
11. The interconnect of claim 1 , wherein the at least one control signal line includes at least one negative conductance device.
12. The interconnect of claim 11 , wherein the at least one control signal line includes a pair of differential signal lines for a control signal.
13. The interconnect of claim 1 , wherein the at least one data signal line includes a pair of differential signal lines for a data signal.
14. The interconnect of claim 1 , wherein the interconnect is included in an integrated circuit chip.
15. A computer system, comprising:
a processor; and
memory;
wherein the processor includes at least one interconnect comprising:
at least one control signal line;
at least one data signal line; and
at least one variable capacitor coupled to the at least one control signal line and the at least one data signal line, wherein the capacitance of the variable capacitor is configured to be controlled by a control signal on the control signal line so that a velocity of a data signal transmitted on the at least one data signal line is determined by the value of the capacitance of the variable capacitor, wherein the control signal comprises a clock signal.
16. The computer system of claim 15 , including at least one negative conductance device configured to restore a signal level of a signal transmitted on the at least one data signal line.
17. The computer system of claim 15 , wherein the interconnect is a transmission line.
18. The computer system of claim 17 , wherein the transmission line is operating in an inductance-capacitance (LC) mode.
19. The computer system of claim 15 , wherein the variable capacitor is configured to provide energy gain on the data signal when the clock signal changes.