Semiconductor photodetectors
In one aspect, a method includes forming a pit in a top surface of a substrate by removing a portion of the substrate and growing a semiconductor material with a bottom surface on the pit, the semiconductor material different than the material of the substrate. The pit has a base recessed in the top surface of the substrate. In another aspect, a structure includes a substrate having a top surface, the substrate including at least one pit having a base lower than the top surface of the substrate, and a semiconductor material having a bottom surface formed on the base of the pit.
1. A method comprising:
forming a pit in a top surface of a semiconductor substrate by removing a portion of the semiconductor substrate, the pit having a base recessed in the top surface of the semiconductor substrate;
fabricating an integrated circuit on the top surface of the semiconductor substrate, the integrated circuit comprising at least one layer of metal interconnects; and
growing a semiconductor material with a bottom surface on the base of the pit, a top surface of the semiconductor material being higher than the top surface of the semiconductor substrate and lower than a bottom surface of a lowest layer of metal interconnects, wherein the semiconductor material comprises a photodetector.
2. The method of claim 1 , further comprising forming active electronic components on the top surface of the substrate, the active electronic components electrically coupled to the photodetector.
3. The method of claim 1 , further comprising doping at least a portion of the base of the pit prior to growing the semiconductor material.
4. The method of claim 3 , wherein the at least a portion of the base of the pit is configured to be an electrode of the semiconductor material.
5. The method of claim 1 , further comprising:
forming a dielectric layer on top of at least a portion of the substrate prior to growing the semiconductor material, the portion of the substrate including the pit; and
generating a hole in the dielectric layer in the region of the pit,
wherein the semiconductor material is grown in the hole in the dielectric layer.
6. The method of claim 5 , wherein the dielectric layer comprises at least one of silicon dioxide (SiO 2 ), silicon oxide (SiO x ), silicon nitride (Si x N y ), or silicon oxynitride (SiO x N y ).
7. The method of claim 5 , wherein the dielectric layer comprises a plurality of sublayers, each sublayer including at least one of silicon dioxide (SiO 2 ), silicon oxide (SiO x ), silicon nitride (Si x N y ), or silicon oxynitride (SiO x N y ).
8. The method of claim 1 , wherein the pit is formed by at least one of dry chemical etching, wet chemical etching, dry thermal oxidation, or wet thermal oxidation.
9. The method of claim 1 , wherein forming the pit comprises:
depositing a mask on the top surface of the substrate, the mask defining the portion of the substrate to be removed;
oxidizing the portion of the substrate to be removed by wet or dry oxidation; and
removing at least a part of an oxide formed by the oxidation of the portion of the substrate.
10. The method of claim 9 , wherein the oxide is removed by chemical mechanical polishing.
11. The method of claim 9 , wherein the oxide is removed by at least one of wet chemical etching or dry chemical etching.
12. The method of claim 9 , wherein the mask comprises at least one of silicon nitride (Si x N y ), silicon oxynitride (SiO x N y ), silicon dioxide (SiO 2 ), or silicon oxide (SiO x ).
13. The method of claim 1 , wherein the integrated circuit is fabricated using CMOS processing or CMOS compatible processing.
14. The method of claim 1 , wherein the step of growing the semiconductor material occurs after front-end processing of the integrated circuit and prior to back-end processing of the integrated circuit.
15. The method of claim 14 , wherein front-end processing comprises fabricating at least one metal-oxide-semiconductor (MOS) transistor.
16. The method of claim 15 , wherein the bottom surface of the semiconductor material is lower than a bottom surface of a gate oxide of the at least one MOS transistor.
17. The method of claim 16 , wherein the bottom surface of the semiconductor material is at least 50 nm lower than the bottom surface of the gate oxide of the at least one MOS transistor.
18. The method of claim 16 , wherein the bottom surface of the semiconductor material is at least 200 nm lower than the bottom surface of the gate oxide of the at least one MOS transistor.
19. The method of claim 15 , wherein a top surface of the semiconductor material is lower than a top surface of the at least one MOS transistor.
20. The method of claim 14 , wherein back-end processing comprises fabricating at least one layer of metal interconnects.
21. The method of claim 1 , further comprising growing polysilicon or amorphous silicon on top of the semiconductor material.
22. The method of claim 21 , further comprising doping at least a portion of the polysilicon or amorphous silicon.
23. The method of claim 22 , wherein the at least a portion of the polysilicon or amorphous silicon is configured to be an electrode of the semiconductor material.
24. The method of claim 1 , further comprising growing polysilicon or amorphous silicon on at least one side of the semiconductor material.
25. The method of claim 1 , wherein the semiconductor material comprises Ge or SiGe.
26. The method of claim 1 , wherein the semiconductor material is grown to a thickness of at least 0.5 μm.
27. The method of claim 1 , wherein the substrate comprises silicon or silicon-on-insulator.
28. A structure, comprising:
a semiconductor substrate having a top surface, the semiconductor substrate including at least one pit having a base lower than the top surface of the semiconductor substrate; an integrated circuit fabricated on the top surface of the semiconductor substrate, the integrated circuit comprising at least one layer of metal interconnects; and
a semiconductor material having a bottom surface formed on the base of the pit, a top surface of the semiconductor material being higher than the top surface of the semiconductor substrate and lower than a bottom surface of a lowest layer of metal interconnects, wherein the semiconductor material comprises a photodetector.
29. The structure of claim 28 , further comprising active electronic components formed on the top surface of the substrate, the active electronic components electrically coupled to the photodetector.
30. The structure of claim 29 , wherein at least a portion of the base of the pit is doped.
31. The structure of claim 30 , wherein at least a portion of the base of the pit is configured to be an electrode of the semiconductor material.
32. The structure of claim 28 , wherein an efficiency of the photodetector is at least 95%.
33. The structure of claim 28 , wherein the semiconductor material comprises Ge or SiGe.
34. The structure of claim 28 , wherein the semiconductor material is at least 0.5 μm thick.
35. The structure of claim 28 , wherein the integrated circuit comprises at least one MOS transistor.
36. The structure of claim 35 , wherein the top surface of the semiconductor material is lower than a top surface of the at least one MOS transistor.
37. The structure of claim 28 , further comprising a layer of an insulator substantially covering the substrate.
38. The structure of claim 28 , wherein the substrate comprises silicon or silicon-on-insulator.
39. The structure of claim 28 , further comprising a layer of polysilicon or amorphous silicon on top of the semiconductor material.
40. The structure of claim 39 , wherein at least a portion of the polysilicon or amorphous silicon is doped.
41. The structure of claim 40 , wherein the at least a portion of the polysilicon or amorphous silicon is configured to be an electrode of the semiconductor material.
42. The structure of claim 28 , further comprising a layer of polysilicon or amorphous silicon on at least one side of the semiconductor material.
43. An electro-optical system comprising:
at least one integrated device including:
a photodetector body having a bottom surface formed on the base of a pit in a semiconductor substrate; and
active electronic components fabricated on the semiconductor substrate and electrically coupled to the photodetector body,
the photodetector body having a thickness selected such that a top surface of the photodetector body is higher than a top surface of the semiconductor substrate and lower than a metallization layer of the active electronic components.
44. The electro-optical system of claim 43 , further comprising an optical fiber coupled to the photodetector body.
45. The electro-optical system of claim 43 , comprising a plurality of integrated devices.
46. The electro-optical system of claim 43 , wherein the active electronic components are configured to amplify a signal detected by the photodetector body.
47. The electro-optical system of claim 46 , wherein the active electronic components are further configured to reshape the signal detected by the photodetector body.
48. The electro-optical system of claim 43 , wherein the active electronic components include a digital microprocessor.
49. The structure of claim 28 , wherein the semiconductor material comprises a photodetector body of a photodetector.
50. The structure of claim 28 , further comprising a contact layer on the top surface of the semiconductor material and below the bottom surface of the lowest layer of metal interconnects.
51. The structure of claim 50 , further comprising a layer of an insulator substantially covering at least a portion of the base of the pit and at least a portion of the top surface of the semiconductor substrate.
52. The structure of claim 51 , further comprising conducting material forming a conducting path between the lowest layer of metal interconnects and the contact layer on the top surface of the semiconductor material.