Cross link multiplexer bus
A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce the signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. Preferably, the destination port is in a first cross link multiplexer, the origin port is in a second cross link multiplexer, and the first cross link multiplexer is configured to convey the signal toward the second cross link multiplexer in more than one direction. In an embodiment, the signal is capable of being represented as a series of characters, and a character is capable of being represented as a number of bits. Preferably, the plurality of cross link multiplexers includes a delay buffer to delay conveyance of a first bit so that it remains substantially synchronized with a second bit. Preferably, the set of interconnects includes a first interconnect to convey the first bit and a second interconnect to convey the second bit. The lengths of the first and the second interconnects are substantially equal.
1. A cross link multiplexer bus, comprising:
a plurality of multiplexers; and
a plurality of interconnects coupled between adjacent pairs of multiplexers from among the plurality of multiplexers;
wherein a first multiplexer from among the plurality of multiplexers is configured to convey a signal toward a second multiplexer from among the plurality of multiplexers in a first direction by a first set of interconnects from among the plurality of interconnects coupled to a third multiplexer from among the plurality of multiplexers and the first multiplexer is configured to convey the signal toward the second multiplexer in a second direction by a second set of interconnects from among the plurality of interconnects coupled other than to the third multiplexer;
wherein the plurality of multiplexers are configured to delay conveyance of a first bit of the signal by a gate delay time;
wherein the plurality of interconnects are configured to delay conveyance of a second bit of the signal by a path delay time; and
wherein the gate delay time and the path delay time are set so that the first bit remains substantially synchronized with the second bit.
2. The cross link multiplexer bus of claim 1 , wherein the plurality of cross link multiplexers are arranged in a substantially circular configuration.
3. The cross link multiplexer bus of claim 1 , wherein the plurality of cross link multiplexers are arranged in a substantially spherical configuration.
4. The cross link multiplexer bus of claim 1 , further comprising:
at least one delay buffer configured to delay conveyance of the signal.
5. The cross link multiplexer bus of claim 4 , wherein the at least one delay buffer is a series of delay buffers.
6. The cross link multiplexer bus of claim 4 , wherein the plurality of interconnects are configured to convey the first bit through the at least one delay buffer and to bypass the first bit around the at least one delay buffer.
7. A cross link multiplexer bus, comprising:
a plurality of multiplexers; and
a plurality of interconnects coupled between adjacent pairs of multiplexers from among the plurality of multiplexers;
wherein the plurality of multiplexers are configured to delay conveyance of a first bit of a signal by a gate delay time;
wherein the plurality of interconnects are configured to delay conveyance of a second bit of the signal by a path delay time;
wherein the gate delay time and the path delay time are set so that the first bit remains substantially synchronized with the second bit; and
wherein a first multiplexer from among the plurality of multiplexers is configured to process the signal if the signal is formatted according to a first communications protocol and a second multiplexer from among the plurality of multiplexers is configured to process the signal if the signal is formatted according to a second communications protocol.
8. The cross link multiplexer bus of claim 7 , wherein the plurality of cross link multiplexers are arranged in a substantially circular configuration.
9. The cross link multiplexer bus of claim 7 , wherein the plurality of cross link multiplexers are arranged in a substantially spherical configuration.
10. The cross link multiplexer bus of claim 7 , further comprising:
at least one delay buffer configured to delay conveyance of the signal.
11. The cross link multiplexer bus of claim 10 , wherein the at least one delay buffer is a series of delay buffers.
12. The cross link multiplexer bus of claim 10 , wherein the plurality of cross link interconnects are configured to convey the first bit through the at least one delay buffer and to bypass the first bit around the at least one delay buffer.
13. A cross link multiplexer bus, comprising:
a plurality of multiplexers, each of the plurality of multiplexers being arranged to be adjacent to more than one multiplexer from among the plurality of multiplexers and to be substantially equidistant from all of its adjacent multiplexers; and
wherein a first multiplexer from among the plurality of multiplexers is configured to convey a signal toward a second multiplexer from among the plurality of multiplexers in a first direction via a first set of interconnects from among a plurality of interconnects and the first multiplexer is configured to convey the signal toward the second multiplexer in a second direction via a second set of interconnects from among the plurality of interconnects, the second direction being substantially different from the first direction; and
wherein the first multiplexer is configured to process the signal if the signal is formatted according to a first communications protocol and the second multiplexer is configured to process the signal if the signal is formatted according to a second communications protocol.
14. The cross link multiplexer bus of claim 13 , wherein the plurality of cross link multiplexers are arranged in a substantially circular configuration.
15. The cross link multiplexer bus of claim 13 , wherein the plurality of cross link multiplexers are arranged in a substantially spherical configuration.
16. The cross link multiplexer bus of claim 13 , further comprising:
at least one delay buffer configured to delay conveyance of the signal.
17. The cross link multiplexer bus of claim 16 , wherein the at least one delay buffer is a series of delay buffers.
18. The cross link multiplexer bus of claim 16 , wherein the plurality of cross link interconnects are configured to convey the first bit through the at least one delay buffer and to bypass the first bit around the at least one delay buffer.
19. The cross link multiplexer bus of claim 13 , wherein the first communications protocol is different from the second communications protocol.
20. The cross link multiplexer bus of claim 13 , wherein the first communications protocol represents a parallel formatted protocol and the second communications protocol represents a serial formatted protocol.
21. The cross link multiplexer bus of claim 13 , wherein the second multiplexer is coupled to a third multiplexer from among the plurality of multiplexers, wherein the first direction represents conveyance of the signal from the first multiplexer to the second multiplexer in a direction toward the third and the second direction represents conveyance of the signal from the first multiplexer to the second multiplexer in a direction away from the third multiplexer.