Mitigation of plating stub resonance by controlling surface roughness
View Patent ↗Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.
1. A method, comprising:
forming a signal interconnect on a substrate of a circuit board;
forming a signal trace extending from near a chip mounting location of the circuit board to the signal interconnect;
forming a plating stub extending from the signal interconnect to a periphery of the substrate along the exterior surface of the circuit board; and
altering the as-formed plating stub to increase the surface roughness of the plating stub.
2. The method of claim 1 , wherein the step of altering the as-formed plating stub to increase the surface roughness of the plating stub comprises selectively removing material from the plating stub using a laser.
3. The method of claim 1 , wherein the step of altering the as-formed plating stub to increase the surface roughness of the plating stub comprises etching the plating stub with chemicals.
4. The method of claim 1 , wherein the step of altering the as-formed plating stub to increase the surface roughness of the plating stub comprises forming surface deviations of between about five to fifteen micrometers.
5. The method of claim 1 , wherein the step of altering the as-formed plating stub to increase the surface roughness of the plating stub comprises forming surface deviations of up to half the thickness of the as-formed plating stub.
6. The method of claim 1 , further comprising:
mounting a chip to the substrate at the chip mounting location; and
connecting a bond pad on the chip to the signal trace using a bond wire.
7. The method of claim 1 , further comprising:
electrically connecting the signal interconnect to the ball of a ball grid array.