Semiconductor device and system
View Patent ↗First and second data output circuits obtain corresponding parts of read data of a storage circuit to output to first and second input/output pads in a second test mode. First and second data input circuits obtain output data of the first and second data output circuits via the first and second input/output pads to output in the second test mode. A comparison object selection circuit selects output data of the first and second data input circuits to output in the second test mode. A judging circuit performs a test judgment by comparing output data of the comparison object selection circuit with expected value data and outputs a test result signal in the second test mode.
1. A semiconductor device, comprising:
a storage circuit performing data reading or data writing according to an external control signal in a normal mode, and performing data reading or data writing according to an internal control signal in a first test mode and a second test mode;
a self-test circuit generating the internal control signal, test data to be used as write data of the storage circuit and expected value data to be compared with read data of the storage circuit in the first test mode and the second test mode;
a first data output circuit obtaining a corresponding part of the read data of the storage circuit and outputting the corresponding part of the read data to a first input/output pad in the normal mode and the second test mode;
a first data input circuit obtaining a corresponding part of the write data of the storage circuit via the first input/output pad in the normal mode, and obtaining output data of the first data output circuit via the first input/output pad in the second test mode;
a second data output circuit obtaining a corresponding part of the read data of the storage circuit and outputting the corresponding part of the read data to a second input/output pad in the normal mode and the second test mode;
a second data input circuit obtaining a corresponding part of the write data of the storage circuit via the second input/output pad in the normal mode, and obtaining output data of the second data output circuit via the second input/output pad in the second test mode;
a comparison object selection circuit selecting the read data of the storage circuit in the first test mode, and selecting data including output data of the first data input circuit and output data of the second data input circuit in the second test mode;
a judging circuit performing a test judgment by comparing output data of the comparison object selection circuit with the expected value data and outputting a test result signal in the first test mode and the second test mode; and
a test result output circuit obtaining the test result signal and outputting the test result signal to an output pad in the first test mode and the second test mode.
2. The semiconductor device according to claim 1 , further comprising:
a control signal output circuit obtaining the internal control signal and outputting the internal control signal to an input pad in the second test mode;
a control signal input circuit obtaining the external control signal via the input pad in the normal mode, and obtaining an output signal of the control signal output circuit via the input pad in the second test mode; and
a control signal selection circuit selecting the internal control signal in the first test mode, and selecting an output signal of the control signal input circuit in the normal mode and the second test mode, wherein
the storage circuit performs data reading or data writing according to an output signal of the control signal selection circuit.
3. The semiconductor device according to claim 2 , wherein
a drivability of the control signal output circuit is smaller than drivabilities of the first data output circuit, the second data output circuit and the test result output circuit.
4. The semiconductor device according to claim 1 , wherein
the external control signal and the internal control signal comprise an address signal indicating a destination to be accessed.
5. The semiconductor device according to claim 1 , wherein
the external control signal and the internal control signal comprise a command signal indicating data reading or data writing.
6. The semiconductor device according to claim 1 , wherein
the external control signal and the internal control signal comprise a clock signal defining an operation timing of data reading or data writing.
7. The semiconductor device according to claim 1 , wherein:
the storage circuit, the self-test circuit, the first data output circuit, the first data input circuit, the second data output circuit, the second data input circuit, the judging circuit and the test result output circuit are commonly mounted on one of a plurality of semiconductor chips to be housed in a same package; and
at least one of the input pad, the first input/output pad and the second input/output pad is coupled to a pad of another semiconductor chip without being coupled to an external pin of the package.
8. The semiconductor device according to claim 1 , wherein
the storage circuit includes a plurality of memory cells.
9. The semiconductor device according to claim 1 , wherein
the storage circuit includes a plurality of registers.
10. A semiconductor device, comprising:
a storage circuit performing data reading or data writing according to an external control signal in a normal mode, and performing data reading or data writing according to an internal control signal in a first test mode and a second test mode;
a self-test circuit generating the internal control signal, test data to be used as write data of the storage circuit and expected value data to be compared with read data of the storage circuit in the first test mode and the second test mode;
a first data output circuit obtaining a corresponding part of the read data of the storage circuit and outputting the corresponding part of the read data to a first input/output pad in the normal mode;
a first data input circuit obtaining a corresponding part of the write data of the storage circuit via the first input/output pad in the normal mode;
a second data output circuit obtaining a corresponding part of the read data of the storage circuit and outputting the corresponding part of the read data to a second input/output pad in the normal mode and the second test mode;
a second data input circuit obtaining a corresponding part of the write data of the storage circuit via the second input/output pad in the normal mode, and obtaining output data of the second data output circuit via the second input/output pad in the second test mode;
a comparison object selection circuit selecting the read data of the storage circuit in the first test mode, and selecting data including the corresponding part in the first input/output pad of the read data of the storage circuit and output data of the second data input circuit in the second test mode;
a judging circuit performing a test judgment by comparing output data of the comparison object selection circuit with the expected value data and outputting a test result signal in the first test mode and the second test mode; and
a test result output circuit obtaining the test result signal and outputting the test result signal to an output pad in the first test mode and the second test mode.
11. A semiconductor device, comprising:
a storage circuit performing data reading or data writing according to an external control signal in a normal mode, a first test mode and a second test mode;
a first data output circuit obtaining a corresponding part of read data of the storage circuit and outputting the corresponding part of the read data to a first input/output pad in the normal mode and the second test mode;
a first data input circuit obtaining a corresponding part of write data of the storage circuit via the first input/output pad in the normal mode, obtaining compressed data corresponding to the write data of the storage circuit via the first input/output pad in the first test mode and the second test mode, and obtaining output data of the first data output circuit via the first input/output pad in the second test mode;
a second data output circuit obtaining a corresponding part of the read data of the storage circuit and outputting the corresponding part of the read data to a second input/output pad in the normal mode and the second test mode;
a second data input circuit obtaining a corresponding part of the write data of the storage circuit via the second input/output pad in the normal mode, and obtaining output data of the second data output circuit via the second input/output pad in the second test mode;
a compression object selection circuit selecting the read data of the storage circuit in the first test mode, and selecting data including output data of the first data input circuit and output data of the second data input circuit in the second test mode;
a data compression circuit compressing output data of the compression object selection circuit in the first test mode and the second test mode; and
a compression result output circuit obtaining output data of the data compression circuit and outputting the output data to an output pad in the first test mode and the second test mode.
12. A semiconductor device, comprising:
a storage circuit performing data reading or data writing according to an external control signal in a normal mode, a first test mode and a second test mode;
a first data output circuit obtaining input data and outputting the input data to a first input/output pad in the normal mode, the first test mode and the second test mode;
a first data input circuit obtaining a corresponding part of write data of the storage circuit via the first input/output pad in the normal mode, and obtaining compressed data corresponding to the write data of the storage circuit via the first input/output pad in the first test mode and the second test mode;
a second data output circuit obtaining a corresponding part of read data of the storage circuit and outputting the corresponding part of the read data to a second input/output pad in the normal mode and the second test mode;
a second data input circuit obtaining a corresponding part of the write data of the storage circuit via the second input/output pad in the normal mode, and obtaining output data of the second data output circuit via the second input/output pad in the second test mode;
a compression object selection circuit selecting the read data of the storage circuit in the first test mode, and selecting data including the corresponding part in the first input/output pad of the read data of the storage circuit and output data of the second data output circuit in the second test mode;
a data compression circuit compressing output data of the compression object selection circuit in the first test mode and the second test mode; and
an output object selection circuit selecting the corresponding part in the first input/output pad of the read data of the storage circuit as the input data of the first data output circuit in the normal mode, and selecting output data of the data compression circuit as the input data of the first data output circuit in the first test mode and the second test mode.
13. A semiconductor device, comprising:
a storage circuit performing data reading or data writing according to an external control signal in a normal mode, and performing data reading or data writing according to an internal control signal in a first test mode and a second test mode;
a self-test circuit generating the internal control signal, test data to be used as write data of the storage circuit and expected value data to be compared with read data of the storage circuit in the first test mode and the second test mode;
a first data selection circuit selecting a corresponding part of the read data of the storage circuit in the normal mode, and selecting a corresponding part of the test data in the second test mode;
a first data output circuit obtaining output data of the first data selection circuit and outputting the output data to a first input/output pad in the normal mode and the second test mode;
a first data input circuit obtaining a corresponding part of the write data of the storage circuit via the first input/output pad in the normal mode, and obtaining output data of the first data output circuit via the first input/output pad as the corresponding part of the write data of the storage circuit in the second test mode;
a second data selection circuit selecting a corresponding part of the read data of the storage circuit in the normal mode, and selecting a corresponding part of the test data in the second test mode;
a second data output circuit obtaining output data of the second data selection circuit to and outputting the output data to a second input/output pad in the normal mode and the second test mode;
a second data input circuit obtaining a corresponding part of the write data of the storage circuit via the second input/output pad in the normal mode, and obtaining output data of the second data output circuit via the second input/output pad as the corresponding part of the write data of the storage circuit in the second test mode;
a judging circuit performing a test judgment by comparing the read data of the storage circuit with the expected value data and outputting a test result signal in the first test mode and the second test mode; and
a test result output circuit obtaining the test result signal and outputting the test result signal to an output pad in the first test mode and the second test mode.
14. A system comprising a semiconductor device, comprising:
a storage circuit performing data reading or data writing according to an external control signal in a normal mode, and performing data reading or data writing according to an internal control signal in a first test mode and a second test mode;
a self-test circuit generating the internal control signal, test data to be used as write data of the storage circuit and expected value data to be compared with read data of the storage circuit in the first test mode and the second test mode;
a first data output circuit obtaining a corresponding part of the read data of the storage circuit and outputting the corresponding part of the read data to a first input/output pad in the normal mode and the second test mode;
a first data input circuit obtaining a corresponding part of the write data of the storage circuit via the first input/output pad in the normal mode, and obtaining output data of the first data output circuit via the first input/output pad in the second test mode;
a second data output circuit obtaining a corresponding part of the read data of the storage circuit and outputting the corresponding part of the read data to a second input/output pad in the normal mode and the second test mode;
a second data input circuit obtaining a corresponding part of the write data of the storage circuit via the second input/output pad in the normal mode, and obtaining output data of the second data output circuit via the second input/output pad in the second test mode;
a comparison object selection circuit selecting the read data of the storage circuit in the first test mode, and selecting data including output data of the first data input circuit and output data of the second data input circuit in the second test mode;
a judging circuit performing a test judgment by comparing output data of the comparison object selection circuit with the expected value data and outputting a test result signal in the first test mode and the second test mode; and
a test result output circuit obtaining the test result signal and outputting the test result signal to an output pad in the first test mode and the second test mode.
15. A system comprising a semiconductor device, comprising:
a storage circuit performing data reading or data writing according to an external control signal in a normal mode, and performing data reading or data writing according to an internal control signal in a first test mode and a second test mode;
a self-test circuit generating the internal control signal, test data to be used as write data of the storage circuit and expected value data to be compared with read data of the storage circuit in the first test mode and the second test mode;
a first data output circuit obtaining a corresponding part of the read data of the storage circuit and outputting the corresponding part of the read data to a first input/output pad in the normal mode;
a first data input circuit obtaining a corresponding part of the write data of the storage circuit via the first input/output pad in the normal mode;
a second data output circuit obtaining a corresponding part of the read data of the storage circuit and outputting the corresponding part of the read data to a second input/output pad in the normal mode and the second test mode;
a second data input circuit obtaining a corresponding part of the write data of the storage circuit via the second input/output pad in the normal mode, and obtaining output data of the second data output circuit via the second input/output pad in the second test mode;
a comparison object selection circuit selecting the read data of the storage circuit in the first test mode, and selecting data including the corresponding part in the first input/output pad of the read data of the storage circuit and output data of the second data input circuit in the second test mode;
a judging circuit performing a test judgment by comparing output data of the comparison object selection circuit with the expected value data and outputting a test result signal in the first test mode and the second test mode; and
a test result output circuit obtaining the test result signal and outputting the test result signal to an output pad in the first test mode and the second test mode.
16. A system comprising a semiconductor device, comprising:
a storage circuit performing data reading or data writing according to an external control signal in a normal mode, a first test mode and a second test mode;
a first data output circuit obtaining a corresponding part of read data of the storage circuit and outputting the corresponding part of the read data to a first input/output pad in the normal mode and the second test mode;
a first data input circuit obtaining a corresponding part of write data of the storage circuit via the first input/output pad in the normal mode, obtaining compressed data corresponding to the write data of the storage circuit via the first input/output pad in the first test mode and the second test mode, and obtaining output data of the first data output circuit via the first input/output pad in the second test mode;
a second data output circuit obtaining a corresponding part of the read data of the storage circuit and outputting the corresponding part of the read data to a second input/output pad in the normal mode and the second test mode;
a second data input circuit obtaining a corresponding part of the write data of the storage circuit via the second input/output pad in the normal mode, and obtaining output data of the second data output circuit via the second input/output pad in the second test mode;
a compression object selection circuit selecting the read data of the storage circuit in the first test mode, and selecting data including output data of the first data input circuit and output data of the second data input circuit in the second test mode;
a data compression circuit compressing output data of the compression object selection circuit in the first test mode and the second test mode; and
a compression result output circuit obtaining output data of the data compression circuit and outputting the output data to an output pad in the first test mode and the second test mode.
17. A system comprising a semiconductor device, comprising:
a storage circuit performing data reading or data writing according to an external control signal in a normal mode, a first test mode and a second test mode;
a first data output circuit obtaining input data and outputting the input data to a first input/output pad in the normal mode, the first test mode and the second test mode;
a first data input circuit obtaining a corresponding part of write data of the storage circuit via the first input/output pad in the normal mode, and obtaining compressed data corresponding to the write data of the storage circuit via the first input/output pad in the first test mode and the second test mode;
a second data output circuit obtaining a corresponding part of read data of the storage circuit and outputting the corresponding part of the read data to a second input/output pad in the normal mode and the second test mode;
a second data input circuit obtaining a corresponding part of the write data of the storage circuit via the second input/output pad in the normal mode, and obtaining output data of the second data output circuit via the second input/output pad in the second test mode;
a compression object selection circuit selecting the read data of the storage circuit in the first test mode, and selecting data including the corresponding part in the first input/output pad of the read data of the storage circuit and output data of the second data output circuit in the second test mode;
a data compression circuit compressing output data of the compression object selection circuit in the first test mode and the second test mode; and
an output object selection circuit selecting the corresponding part in the first input/output pad of the read data of the storage circuit as the input data of the first data output circuit in the normal mode, and selecting output data of the data compression circuit as the input data of the first data output circuit in the first test mode and the second test mode.
18. A system comprising a semiconductor device, comprising:
a storage circuit performing data reading or data writing according to an external control signal in a normal mode, and performing data reading or data writing according to an internal control signal in a first test mode and a second test mode;
a self-test circuit generating the internal control signal, test data to be used as write data of the storage circuit and expected value data to be compared with read data of the storage circuit in the first test mode and the second test mode;
a first data selection circuit selecting a corresponding part of the read data of the storage circuit in the normal mode, and selecting a corresponding part of the test data in the second test mode;
a first data output circuit obtaining output data of the first data selection circuit and outputting the output data to a first input/output pad in the normal mode and the second test mode;
a first data input circuit obtaining a corresponding part of the write data of the storage circuit via the first input/output pad in the normal mode, and obtaining output data of the first data output circuit via the first input/output pad as the corresponding part of the write data of the storage circuit in the second test mode;
a second data selection circuit selecting a corresponding part of the read data of the storage circuit in the normal mode, and selecting a corresponding part of the test data in the second test mode;
a second data output circuit obtaining output data of the second data selection circuit and outputting the output data to a second input/output pad in the normal mode and the second test mode;
a second data input circuit obtaining a corresponding part of the write data of the storage circuit via the second input/output pad in the normal mode, and obtaining output data of the second data output circuit via the second input/output pad as the corresponding part of the write data of the storage circuit in the second test mode;
a judging circuit performing a test judgment by comparing the read data of the storage circuit with the expected value data and outputting a test result signal in the first test mode and the second test mode; and
a test result output circuit obtaining the test result signal and outputting the test result signal to an output pad in the first test mode and the second test mode.