IP Library Granted Patent US 7,977,125
Granted Patent B2
US 7,977,125 · App. 12/255,577 · Granted Jul 12, 2011

Display apparatus and method of manufacturing the same

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Quick Facts
Patent No.
US 7,977,125
App. No.
12/255,577
Granted
Jul 12, 2011
Kind
B2
Abstract

In a display apparatus and a method of manufacturing the display apparatus, a gate line, a data line, and a plurality of layers are formed on an array substrate on which a pixel area, a pad area, and a peripheral area are defined. During the forming processes of the gate line, the data line, and the layers, the gate line and the data line are partially exposed in the peripheral area, or contact portions formed on the gate line and the data line in the peripheral area are exposed. Thus, the gate line and the data line may be tested using the contact portions as electrical terminals during the manufacturing process of the display apparatus.

Claims (36)

1. A method of manufacturing a display apparatus, comprising:

preparing a first substrate on which a pixel area, a first pad area, and a second pad area are defined;

forming a gate line on the first substrate;

forming a first insulating layer pattern on the gate line;

forming a data line on the first substrate;

forming a first contact portion that is arranged above the gate line and electrically connected to the gate line in a first peripheral area spaced apart from the first pad area to form a first test pad;

testing the gate line using the first contact portion as a terminal;

forming a second contact portion arranged above the first contact portion and electrically connected to the first contact portion and the gate line;

forming a second insulating layer pattern on the data line;

forming a pixel electrode in the pixel area;

testing the gate line using the second contact portion as a terminal; and

combining a second substrate on which a common electrode is formed with the first substrate.

2. The method of claim 1 , wherein the first contact portion is formed by a same process as the data line and comprises a same material as the data line, and the second contact portion is formed by a same process as the pixel electrode and comprises a same material as the pixel electrode.

3. The method of claim 1 , further comprising forming a gate pad in the first pad area, and

wherein the gate pad is formed by:

forming a third contact portion arranged above the gate line in the first pad area and electrically connected to the gate line, the third contact portion being formed by a same process as the data line and comprising a same material as the data line; and

forming a fourth contact portion arranged above the third contact portion and electrically connected to the third contact portion and the gate line, the fourth contact portion being formed by a same process as the pixel electrode and comprising a same material as the pixel electrode.

4. The method of claim 1 , further comprising:

forming a fifth contact portion arranged above the data line in a second peripheral area that is spaced apart from the second pad area, the fifth contact portion being electrically connected to the data line to form a second test pad, and

wherein the fifth contact portion is formed through a same process as the pixel electrode and comprises a same material as the pixel electrode.

5. The method of claim 4 , further comprising testing the data line using the fifth contact portion as a terminal after the pixel electrode and the fifth contact portion are formed.

6. The method of claim 1 , further comprising forming a data pad in the second pad area,

wherein forming the data pad comprises forming a sixth contact portion above the data line in the second pad area, the sixth contact portion being electrically connected to the data line, and the sixth contact portion being formed through a same process as the pixel electrode and comprising a same material as the pixel electrode.

7. The method of claim 1 , wherein the first substrate comprises a plastic material.

8. A method of manufacturing a display apparatus, the method comprising the following steps:

providing a first substrate comprising a pixel area and a peripheral area;

forming a first conductive layer on the first substrate and patterning the first conductive layer to define gate lines extending in a first direction across the pixel area, each gate line comprising gate electrodes, a gate line test portion located in the peripheral area at a first side of the pixel area and each gate line comprising a gate line bonding portion located in the peripheral area at a second side of the pixel area, the second side of the pixel area being opposite the first side of the pixel area, and a preliminary gate line connected to at least two gate line bonding portions to electrically connect with at least two gate lines;

forming a first insulating layer on the first conductive layer, and patterning the first insulating layer to provide via holes exposing the gate line test portions;

forming semiconductor regions on the first insulating layer above the gate electrodes;

forming a second conductive layer on the first insulating layer and patterning the second conductive layer to define data lines extending in a second direction across the pixel area, the second direction being substantially perpendicular to the first direction, each data line comprising a data line test portion located in the peripheral region at a third side of the pixel area and a data line bonding portion located in the peripheral area at a fourth side of the pixel area, the third side of the pixel area being opposite the fourth side of the pixel area, and a preliminary data line connected to at least two data line bonding portions and thus electrically connected to at least two data lines;

forming a second insulating layer on the second conductive layer and patterning the second insulating layer to provide thru-holes above the gate line test portions and above the data line test portions;

forming a pixel layer on the second insulating layer and patterning the pixel layer to provide pixel electrodes;

applying, after one or more of the steps recited above, a test voltage between first and second gate lines via first and second gate line test line portions; and

removing the preliminary gate line and the preliminary data line.

9. The manufacturing method of claim 8 further comprising:

applying a test voltage between first and second data lines via first and second data line test portions after one or more of the steps of patterning the second conductive layer, patterning the second insulating layer and patterning the pixel layer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2026
From: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
To: LONESTAR CRYSTAL DISPLAY LLC
Reel/Frame 074944/0730 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2022
From: SAMSUNG DISPLAY CO., LTD.
To: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 060778/0487 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 029007/0934 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2008
From: SONG, KEUN-KYU
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 021716/0208 →