SEMICONDUCTOR DEVICE AND ITS FABRICATION PROCESS

1 . A semiconductor device comprising:

(a) a semiconductor chip;

(b) a plurality of leads electrically connected with the semiconductor chip and containing copper as a primary material;

(c) a plating film formed on a surface of each of the plurality of leads, and the plating film containing tin as a primary material and not containing lead; and

(d) a sealant member for sealing the semiconductor chip, wherein

part of each of the plurality of leads is exposed from the sealant member, and

a coefficient of thermal expansion in an in-plane direction of the plating film is lower than a coefficient of thermal expansion of the copper.

2 . The semiconductor device according to claim 1 , wherein

the tin constituting the plating film is a polycrystal having a plurality of grains; and

the plurality of grains include a grain having a (001) plane being parallel to the surface of the plating film.

3 . The semiconductor device according to claim 2 , wherein

when a rate of grains having a (hkl) plane being parallel to the surface of the plating film occupy the volume of the plating film is x(hkl), and an average value of the coefficients of thermal expansion in the in-plane direction of the plating film of the grains having the (hkl) plane being parallel to the surface of the plating film is α(hkl), x(h 1 k 1 l 1 )×α(h 1 k 1 l 1 )+x(h 2 k 2 l 2 )×α(h 2 k 2 l 2 )+ . . . +x(h n k n l n )×α(h n k n l n )≦17.2×10 −6 (where, x(h 1 k 1 l 1 )+x(h 2 k 2 l 2 )+ . . . +x(h n k n l n )=1) is satisfied.

4 . The semiconductor device according to claim 2 , wherein

a gold film or a silver film is formed between the plurality of leads and the plating film.

5 . The semiconductor device according to claim 4 , wherein

the gold film or the silver film is formed so that a (001) plane is parallel to the surface of the plating film.

6 . The semiconductor device according to claim 1 , wherein,

when a crystal structure is analyzed by using X-ray diffraction with respect to the plating film, an intensity peak obtained by X-ray diffraction appears between 0.16 nm and 0.18 nm of a value of crystal plane spacing.

7 . The semiconductor device according to claim 6 , wherein

the intensity peak that appears between 0.16 nm to 0.18 nm of the value of crystal plane spacing is the highest peak.

8 . A semiconductor device comprising:

(a) a semiconductor chip;

(b) a plurality of leads electrically connected with the semiconductor chip and containing copper as a primary material;

(c) a plating film formed on a surface of each of the plurality of leads, and the plating film containing tin as a primary material and not containing lead; and

(d) a sealant member for sealing the semiconductor chip, wherein

part of each of the plurality of leads is exposed from the sealant member, and

the plating film comprises a film having a coefficient of thermal expansion in an in-plane direction of the plating film lower than a coefficient of thermal expansion of the copper.

9 . The semiconductor device according to claim 8 , wherein

the film contained comprised in the plating film and having the coefficient of thermal expansion in the in-plane direction that is lower than the coefficient of thermal expansion of the copper is in direct contact with each of the plurality of leads.

10 . A fabrication process of a semiconductor device comprising the steps of:

(a) preparing a lead frame containing copper as a primary material;

(b) forming a plating film containing tin as a primary material and not containing lead on a surface of each of a plurality of leads formed to the lead frame;

(c) mounting a semiconductor chip on a tab of the lead frame;

(d) connecting the semiconductor chip with the plurality of leads formed to the lead frame by wires;

(e) forming a sealant member by sealing the semiconductor chip; and

(f) cutting the lead frame to separate the sealant body into pieces, wherein

the plating film is formed so that a coefficient of thermal expansion in an in-plane direction of the plating film is lower than a coefficient of thermal expansion of the copper constituting the plurality of leads.

11 . The fabrication process of the semiconductor device according to claim 10 , wherein

the tin constituting the plating film is a polycrystal having a plurality of grains; and

the plating film is formed so that the plurality of grains contain a grain having a (001) plane being parallel to the surface of the plating film.

12 . The fabrication process of the semiconductor device according to claim 11 , wherein

a rate of the grains having a (hkl) plane being parallel to the surface of the plating film occupy the volume of the plating film is x(hkl), and an average value of the coefficients of thermal expansion in the in-plane direction of the plating film of the grains having the (hkl) plane being parallel to the surface of the plating film is α(hkl), the plating film is formed to satisfy x(h 1 k 1 l 1 )×α(h 1 k 1 l 1 )+x(h 2 k 2 l 2 )×α(h 2 k 2 l 2 )+ . . . +x(h n k n l n )×α(h n k n l n )≦17.2×10 −6 (where, x(h 1 k 1 l 1 )+x(h 2 k 2 l 2 )+ . . . +x(h n k n l n )=1).

13 . The fabrication process of the semiconductor device according to claim 10 , wherein

the step (b) includes the steps of:

(b1) forming a gold film or a silver film on the surface of each of the plurality of leads formed to the lead frame; and

(b2) forming the plating film containing tin as a primary material and not containing lead on the gold film or the silver film after the step (b1).

14 . The fabrication process of the semiconductor device according to claim 13 , wherein,

in the step (b1), the gold film or the silver film is formed under a condition such that the (001) plane is parallel to the surface of the plating film.