Method and system for power-state transition controllers
View Patent ↗Power-state transitioning arrangements are implemented using a variety of methods. Using one such method, a power-state transitioning circuit arrangement is implemented having a processing circuit that does not include an arithmetic logic unit. A power-state transition script including instructions from an instruction set is stored in a memory circuit. The processing circuit implements the power-state transition script to facilitate a change in a power-state of another processor circuit.
1. A power-state transitioning circuit arrangement, comprising:
an instruction set;
a power-state-transition script including at least some of the instructions in the instruction set;
a memory circuit structured to store the power-state-transition script; and
a first processing circuit that does not include an arithmetic-logic-unit and is configured to facilitate a change in a power-state of a second processing circuit using the power-state transition script;
wherein the instruction set consists of a write instruction, a delay instruction, a conditional jump instruction and a handshake instruction.
2. The power-state transitioning circuit arrangement of claim 1 , wherein the first processing circuit and the memory circuit are implemented on a single integrated-circuit.
3. The power-state transitioning circuit arrangement of claim 1 , wherein the first processing circuit is structured to facilitate a change in a power-state in response to an input external to the power-state transitioning circuit arrangement.
4. The power-state transitioning circuit arrangement of claim 3 , wherein the power-state-transition script is structured to be modified while the power-state transitioning circuit arrangement is electrically connected to the second processing circuit.
5. The power-state transitioning circuit arrangement of claim 1 , wherein the power-state transitioning circuit arrangement includes a modification of one of a clock frequency and a power supply voltage of the second processing circuit.
6. The power-state transitioning circuit arrangement of claim 1 , wherein the first processing circuit does not contain logical registers.
7. A power-state transitioning processor arrangement, comprising:
an instruction set having a write instruction, a conditional jump instruction, a delay instruction and a handshake instruction;
a configurable memory circuit having stored instructions corresponding to instructions of the instruction set; and
a secondary processor that is structured to facilitate a power-state transition of a main processor circuit using the instructions stored in the memory circuit, the processor being integrated with the main processor circuit.
8. The power-state transitioning processor arrangement of claim 7 , further including a bus interface, a set of input signals and a set of output signals.
9. The power-state transitioning processor arrangement of claim 7 , wherein the instruction set has less than 17 instructions.
10. The power-state transitioning processor arrangement of claim 7 , wherein the secondary processor does not contain an ALU.
11. The power-state transitioning processor arrangement of claim 10 , wherein the secondary processor does not contain logical registers.
12. A system, comprising:
a memory circuit structured to store a power-state-transition script that includes instructions from an instruction set; and
a first processing circuit structured to facilitate a change in a power-state of a second processing circuit using the power-state transition script, the first processing circuit not having an arithmetic-logic-unit;
wherein the instruction set includes a write instruction, a delay instruction, a conditional jump instruction, and a handshake instruction.
13. The system of claim 12 , wherein the instruction set has less than 17 instructions.
14. The system of claim 12 , wherein the first processing circuit does not include an arithmetic logic unit.
15. The system of claim 14 , wherein the first processing circuit does not include logical registers.
16. A power-state transitioning circuit arrangement, comprising:
an instruction set that includes a write instruction, a delay instruction, a conditional jump instruction, and a handshake instruction;
a power-state-transition script including at least some of the instructions in the instruction set;
a memory circuit structured to store the power-state-transition script; and
a first processing circuit that does not include an arithmetic-logic-unit and that is structured to facilitate a change in a power-state of a second processing circuit using the power-state transition script.
17. The power-state transitioning circuit arrangement of claim 16 , wherein the first processing circuit and the memory circuit are implemented on a single integrated-circuit.
18. The power-state transitioning circuit arrangement of claim 16 , wherein the first processing circuit is structured to facilitate a change in a power-state in response to an input external to the power-state transitioning circuit arrangement.
19. The power-state transitioning circuit arrangement of claim 18 , wherein the power-state-transition script can be modified while the power-state transitioning circuit arrangement is electrically connected to the second processing circuit.
20. The power-state transitioning circuit arrangement of claim 16 , wherein the power-state transitioning circuit arrangement includes a modification of one of a clock frequency and a power supply voltage of the second processing circuit.
21. The power-state transitioning circuit arrangement of claim 16 , wherein the first processing circuit does not contain logical registers.