Mask and manufacturing method of a semiconductor device and a thin film transistor array panel using the mask

1. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate line including a gate electrode;

forming a gate insulating layer on the gate line;

forming a semiconductor on the gate insulating layer;

forming a data line including a source electrode and a drain electrode over the semiconductor layer;

depositing a passivation layer on the data line and the drain electrode; and

forming a pixel electrode connected to the drain electrode,

wherein the semiconductor, the data line, and the drain electrode are etched through a photolithography process using one exposure mask,

wherein the exposure mask includes:

a translucent area comprising a translucent layer that generates a phase difference in an incident light passing through the translucent area, the phase difference provided in the range from about −70° to about +70°;

a light blocking opaque area comprising an opaque layer, wherein the opaque area faces the data line and the drain electrode; and

a remaining area other than the translucent area and the light blocking opaque area.

2. The method of claim 1 , wherein:

a photoresist pattern comprising a first portion and a second portion thicker than the first portion is formed during the photolithography process using the exposure mask.

3. The method of claim 2 , wherein:

the first portion faces a channel area between the source electrode and the drain electrode; and

the second portion faces a wire area on the data line and drain electrode.

4. The method of claim 3 , wherein, in a photolithography process:

the wire area is aligned to the light blocking opaque area; and

the channel area is aligned to the translucent area.

5. The method of claim 3 , further comprising: forming ohmic contacts between the data line, the drain electrode, and the semiconductor.

6. The method of claim 5 , wherein the formation of the data line and the drain electrode, the ohmic contactors, and the semiconductor comprises:

depositing an intrinsic silicon layer, an extrinsic silicon layer, and conductor layer on the gate insulating layer;

forming a photoresist including a first portion corresponding to the channel area between the source electrode and the drain electrode, and a second portion corresponding to the wire area on the data line and the drain electrode and thicker than the first portion;

etching the portion of the conductor layer corresponding to a remaining area other than the wire and the channel areas, using the photoresist as an etch mask;

removing the first portion to expose the conductor layer on the channel areas;

etching the intrinsic silicon layer and the extrinsic silicon layer on the remaining area;

etching the conductor layer and the extrinsic silicon layer on the channel areas; and

removing the second portion.

7. The method of claim 1 , wherein the exposing of the photoresist film using the exposure mask by using one of a GH light with wavelength in the range of 400-440 nm, a KrF light with wavelength in the range of 230-260 nm, and a ArF light with wavelength in the range of 180-210 nm.

8. The method of claim 1 , wherein the exposure mask further includes a transparent areas and wherein the translucent area have the transmittance to a range of about 20% and about 40% of the transmittance of the transparent areas.