System and method for fully digital clock divider with non-integer divisor support
View Patent ↗A system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer. Circuitry may be used to ensure that the first clock, or input clock, has a frequency at least equal to the highest of the desired output frequencies. The input clock may be used to generate several output clocks with different frequencies. If one of the output clocks has the same frequency as the input clock, the circuitry can be bypassed. The different clocks may be used to drive parts of a system, each of which may require a different frequency.
1. A system for generating a second clock from a first clock, wherein a ratio of a frequency of the first clock to a frequency of the second clock is a non-integer, the system comprising:
a divider configured to use rising and falling edges of the first clock to generate cycles of the second clock, the cycles of the second clock having a duration of a first number of cycles of the first clock,
wherein the divider is configured to generate other cycles of the second clock, the other cycles having the duration of a second number of cycles of the first clock,
wherein the divider is configured to calculate a first timing error between a time associated with a first edge of the first clock and a time for an edge at the frequency for the second clock,
wherein the divider is configured to calculate a second timing error between a time associated with a second edge of the first clock and the time for an edge at the frequency for the second clock,
wherein the divider is configured to generate an edge at the time of the first edge if the first timing error is less than the second timing error, and
wherein the divider is configured to generate an edge at the time of the second edge if the second timing error is less than the second timing error.
2. The system according to claim 1 , wherein the divider is a digital divider.
3. The system according to claim 1 , wherein the first clock and the second clock are digital clocks.
4. The system according to claim 1 , wherein an absolute difference between the first number and the second number is one.
5. The system according to claim 1 , wherein the second clock is used with video-related content.
6. The system according to claim 1 , wherein the second clock is used for audio-related content.
7. The system according to claim 1 , wherein the divider is configured to add a noise signal to the second clock.
8. The system according to claim 1 , wherein the second clock is used to drive audio circuitry.
9. The system according to claim 1 , wherein the second clock is used to drive video circuitry.
10. The system according to claim 1 , wherein the second clock is used in an audio/video ASIC decoder circuit.
11. The system according to claim 1 , wherein the divider is part of an audio/video synchronization circuit.
12. The system according to claim 1 , wherein the second clock does not have a fifty percent duty cycle.
13. The system according to claim 1 , further comprising:
a phase lock loop having an output that is connected to an input of the divider.
14. The system according to claim 1 , wherein the first clock is used with a video decoder.
15. The system according to claim 14 , wherein the second clock is used with an audio decoder.
16. The system according to claim 15 , wherein the divider, the video decoder and the audio decoder are integrated on an integrated circuit chip.
17. The system according to claim 16 , wherein the integrated circuit chip is an ASIC.
18. The system according to claim 1 , wherein the divider comprises an output generator and a controller.
19. The system according to claim 18 , wherein the output generator receives the first clock and a transition decision from the controller, and wherein the output generator generates the second clock based on the first clock and the transition decision.
20. The system according to claim 18 , where in the controller performs a Bresenham algorithm.
21. The system according to claim 18 , further comprising a second divider that generates a third clock from at least the first clock, wherein a second ratio of the frequency of the first clock to the frequency of the third clock is a non-integer, wherein the second ratio is different from the ratio of the frequency of the first clock to the frequency of the second clock.
22. The system according to claim 18 , wherein the controller receives control data and stores control values, wherein the control values are programmable and are used to create edges in the second clock that correspond to a particular duty cycle.
23. The system according to claim 18 , wherein the controller is configured to calculate the first timing error, and wherein the controller is configured to calculate the second timing error.
24. The system according to claim 1 , wherein the divider is configured to break up a pattern of generated cycles and generated other cycles of the second clock.
25. The system according to claim 24 , wherein the breaking up of the pattern comprises using error diffusion techniques.
26. The system according to claim 24 , wherein the breaking up of the pattern comprises using dithering techniques.