Liquid crystal display and method for manufacturing the same
View Patent ↗A liquid crystal display includes a substrate, a plurality of gate lines formed on the substrate, a plurality of data lines intersecting the gate lines, a plurality of common voltage lines formed in the same layer as the data line and parallel to the data lines and transmitting a common voltage, a plurality of thin film transistors connected to the gate lines and the data lines, and a plurality of pixel electrodes respectively connected to the thin film transistors, arranged in a matrix shape, each of the plurality of pixels including a first edge parallel to the gate lines and a second edge having a shorter length than the first edge and neighboring the first edge.
1. A liquid crystal display comprising:
a substrate;
a plurality of gate lines formed on the substrate;
a plurality of data lines intersecting the gate lines;
a plurality of common voltage lines formed in a layer of the liquid crystal display including the data line and substantially parallel to the data lines;
a plurality of thin film transistors connected to the gate lines and the data lines; and
a plurality of pixel electrodes respectively connected to the thin film transistors, arranged in a matrix shape, each of the plurality of pixels including a first edge substantially parallel to the gate lines and a second edge having a shorter length than the first edge and neighboring the first edge.
2. The liquid crystal display of claim 1 , wherein
the common voltage lines include an expansion electrode overlapping at least a portion of the pixel electrode.
3. The liquid crystal display of claim 2 , wherein
the expansion electrode overlaps a portion of one side of the pixel electrode.
4. The liquid crystal display of claim 2 , wherein
the expansion electrode overlaps an edge portion of the pixel electrode.
5. The liquid crystal display of claim 2 , wherein
a portion of the expansion electrode is disposed between the pixel electrode and a neighboring pixel electrode.
6. The liquid crystal display of claim 1 , wherein
the gate line transverses the pixel electrode in a row direction.
7. The liquid crystal display of claim 6 , wherein
the common voltage lines include a cover electrode covering a portion of the gate line.
8. The liquid crystal display of claim 1 , further comprising
a storage electrode formed in a layer of the liquid crystal display including the gate line, and receiving a data voltage from the thin film transistor.
9. The liquid crystal display of claim 8 , wherein
the common voltage lines include an expansion electrode simultaneously overlapping the storage electrode and the pixel electrode.
10. The liquid crystal display of claim 9 , further comprising:
a gate insulating layer formed between the storage electrode and the common voltage lines; and
a passivation layer formed on the thin film transistor,
wherein the thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode.
11. The liquid crystal display of claim 10 , wherein:
the gate insulating layer and the passivation layer include a first contact hole exposing a portion of the storage electrode;
the passivation layer includes a second contact hole exposing a portion of the drain electrode;
the pixel electrode receives the data voltage from the drain electrode through the second contact hole; and
the storage electrode receives the data voltage from the pixel electrode through the first contact hole.
12. The liquid crystal display of claim 10 , wherein:
the gate insulating layer includes a first contact hole exposing a portion of the storage electrode;
the passivation layer includes a second contact hole exposing a portion of the drain electrode and overlapping the first contact hole;
the pixel electrode receives the data voltage from the drain electrode through the second contact hole; and
the storage electrode receives the data voltage from the drain electrode through the first contact hole.
13. The liquid crystal display of claim 10 , wherein:
the gate insulating layer and the passivation layer include a contact hole simultaneously exposing portions of the drain electrode and the storage electrode; and
the pixel electrode and the storage electrode receive the data voltage from the drain electrode through the contact hole.
14. The liquid crystal display of claim 1 , further comprising
a gate driver connected to the gate lines.
15. The liquid crystal display of claim 14 , wherein
the gate driver includes a plurality of electrical elements disposed in a layer of the liquid crystal display including the gate lines, the data lines, and the thin film transistors.
16. The liquid crystal display of claim 1 , further comprising:
a common electrode facing the pixel electrode,
wherein the pixel electrode comprises a transparent electrode; and
a reflective electrode formed on the transparent electrode and having an opening exposing the transparent electrode.
17. The liquid crystal display of claim 16 , further comprising
a first passivation layer formed under the transparent electrode,
wherein the surfaces of the first passivation layer and the pixel electrode are uneven.
18. The liquid crystal display of claim 17 , wherein
the first passivation layer includes an organic material.
19. The liquid crystal display of claim 17 , further comprising
a second passivation layer formed under the first passivation layer.
20. The liquid crystal display of claim 1 , further comprising:
an upper substrate facing the substrate;
a common electrode formed on the upper substrate; and
a liquid crystal layer interposed between the substrate and the upper substrate, and including liquid crystal molecules,
wherein the pixel electrode or the common electrode includes an inclination direction determining member that determines an inclination direction of the liquid crystal molecules.
21. A method for manufacturing a liquid crystal display comprising:
forming a gate conductor including a gate line and a storage electrode on a substrate;
sequentially forming a gate insulating layer and a semiconductor layer on the gate conductor;
forming a data conductor including a data line, a drain electrode, and a common voltage line substantially parallel to the data line and intersecting the gate line on the semiconductor layer;
forming a passivation layer on the data conductor;
etching the passivation layer and the gate insulating layer to form at least one contact hole exposing the storage electrode and the drain electrode; and
forming a pixel electrode on the passivation layer.
22. The method of claim 21 , wherein:
the contact hole includes a first contact hole exposing the storage electrode and a second contact hole exposing the drain electrode and being separate from the first contact hole;
the first contact hole is formed in the gate insulating layer; and
the second contact hole is formed in the gate insulating layer and the passivation layer.
23. The method of claim 21 , wherein:
the contact hole includes a first contact hole exposing the storage electrode and a second contact hole exposing the drain electrode and overlapping the first contact hole;
the first contact hole is formed in the gate insulating layer; and
the second contact hole is formed in the passivation layer.
24. The method of claim 21 , wherein
the contact hole simultaneously exposes the storage electrode and the drain electrode.
25. The method of claim 21 , wherein:
the forming of the passivation layer includes forming an organic layer to be uneven; and
the forming of the pixel electrode includes forming a transparent electrode and forming a reflective electrode on the transparent electrode, wherein the reflective electrode exposes a portion of the transparent electrode.