IP Library Granted Patent US 8,018,753
Granted Patent B2
US 8,018,753 · App. 12/262,038 · Granted Sep 13, 2011

Memory module including voltage sense monitoring interface

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Quick Facts
Patent No.
US 8,018,753
App. No.
12/262,038
Granted
Sep 13, 2011
Kind
B2
Abstract

Memory devices and systems include a voltage sense line for addressing voltage tolerances across variable loadings. The memory devices and systems comprise a memory module connector with a first plurality of pins coupled to circuitry on a memory module, and a second plurality of pins coupled to power rails on the memory module that enable monitoring of the power rails from external to the memory module.

Claims (14)

1. A memory apparatus comprising: a memory module connector including:

a first plurality of pins coupled to circuitry on a memory module; and

a second plurality of pins coupled to centers of power draw on power rails on the memory module and arranged for monitoring of the power rails from external to the memory module.

2. The apparatus according to claim 1 wherein: the second plurality of pins including voltage sense lines that route signals from the power rails on the memory module for use in power sensing external to the memory module.

3. The apparatus according to claim 1 further comprising: a memory module including:

the memory module connector;

a circuit board coupled to the memory module connector; and

a plurality of integrated circuits mounted to the circuit board and including at least one memory integrated circuit.

4. The apparatus according to claim 1 further comprising:

a plurality of memory modules, ones of the memory module plurality including the memory module connector, a circuit board coupled to the memory module connector, and a plurality of integrated circuits mounted to the circuit board; and

a circuit that combines power signals from the power rails of the plurality of memory modules.

5. The apparatus according to claim 1 further comprising:

a plurality of memory modules, ones of the memory module plurality including the memory module connector, a circuit board coupled to the memory module connector, and a plurality of integrated circuits mounted to the circuit board; and

a circuit that monitors at least one power signal from the power rails of the plurality of memory modules.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 055360/0424 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT 4TH INVENTORS NAME PREVIOUSLY RECORDED AT REEL: 022682 FRAME: 0574. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 9, 2020
From: CARR, DENNIS; CALHOUN, MICHAEL BOZICH; LEE, TEDDY; WARNES, LIDIA; VU, DAN
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 052619/0381 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2009
From: CARR, DENNIS; CALHOUN, MICHAEL BOZICH; LEE, TEDDY; WARNES, LIDLA; VU, DAN
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 022682/0574 →