IP Library Granted Patent US 8,008,966
Granted Patent B2
US 8,008,966 · App. 12/262,057 · Granted Aug 30, 2011

Start-up circuit for generating bandgap reference voltage

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Quick Facts
Patent No.
US 8,008,966
App. No.
12/262,057
Granted
Aug 30, 2011
Kind
B2
Abstract

Disclosed is a start-up circuit that can stably and rapidly start up a bandgap reference voltage generating circuit when the bandgap reference voltage generating circuit is switched from a sleep mode to an operation mode, even if a difference in electrical characteristic, such as DC offset or the like, occurs due to, e.g, a physical difference between input transistors of an operational amplifier.

Claims (15)

1. A start-up circuit which is used in a bandgap reference voltage generating circuit, the start-up circuit comprising:

a first PMOS transistor having a drain connected to a power supply terminal, and a source and a gate connected with each other;

a first NMOS transistor having a drain connected to the source of the first PMOS transistor and a gate connected to a bandgap output terminal;

a second NMOS transistor having a drain connected to a source of the first NMOS transistor, a source connected to a ground terminal, and a gate to which a first mode signal is applied;

a third NMOS transistor having a drain connected to an output terminal of an operational amplifier and a gate connected to the drain of the first NMOS transistor; and

a fourth NMOS transistor having a source connected to the ground terminal, a drain connected to a source of the third NMOS transistor, and a gate to which the first mode signal is applied.

2. The start-up circuit of claim 1 , further comprising:

a fifth NMOS transistor having a drain connected to the bandgap output terminal, a source connected to the ground terminal, and a gate to which a second mode signal is applied, the first mode signal being an inverse of the second mode signal.

3. The start-up circuit of claim 1 , further comprising:

a low pass filter connected to the bandgap output terminal.

4. The start-up circuit of claim 3 , wherein the low pass filter includes a resistor connected in series to the bandgap output terminal and a capacitor connected between the bandgap output terminal and the power supply terminal.

5. The start-up circuit of claim 4 , wherein the resistor and the capacitor each comprise a MOS transistor.

6. The start-up circuit of claim 3 , wherein the lowpass filter comprises a plurality of transistors.

7. The start-up circuit of claim 6 , wherein at least one of the transistors is connected between the bandgap output terminal and the power supply terminal to function as a capacitor and another at least one of the transistors is connected in series to the bandgap output terminal to function as a resistor.

8. The start-up circuit of claim 1 , further comprising a transistor having a drain connected to the bandgap output terminal, a source connected to the ground terminal, and a gate to which the a second mode signal is applied, the first mode signal being an inverse of the second mode signal.

Assignments (7)
CHANGE OF NAME Recorded Nov 19, 2025
From: TESSERA ADVANCED TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.
Reel/Frame 073635/0304 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2015
From: STRATEGIC GLOBAL ADVISORS OF OREGON, INC.
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 035620/0771 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2015
From: DONGBU HITEK CO., LTD.
To: STRATEGIC GLOBAL ADVISORS OF OREGON, INC.
Reel/Frame 035491/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2008
From: CHO, EUN SANG
To: DONGBU HITEK CO., LTD.
Reel/Frame 021772/0222 →