Semiconductor device with suppressed crystal defects in active areas
View Patent ↗A technique that makes it possible to suppress a crystal defect produced in an active area and thereby reduce the fraction defective of semiconductor devices is provided. A first embodiment relates to the planar configuration of SRAM. One of the features of the first embodiment is as illustrated in FIG. 4 . That is, on the precondition that the active areas in n-channel MISFET formation regions are all configured in the isolated structure: the width of the terminal sections is made larger than the width of the central parts of the active areas. For example, the terminal sections are formed in an L shape.
1. A semiconductor device including a plurality of memory cells of SRAM, comprising:
a semiconductor substrate;
an element isolation region formed by filling a trench formed in the semiconductor substrate with an insulating film;
a first active area which is defined by the element isolation region, which is formed by implanting a first conductive impurity into the semiconductor substrate and which extends in a first direction so as to span two or more of said memory cells;
a second active area which is defined by the element isolation region, and which is formed by implanting the first conductive impurity into the semiconductor substrate, and which extends in the first direction so as to span two or more of said memory cells and which is isolated from the first active region by the element isolation region;
a plurality of first n-type MISFETs and a plurality of second n-type MISFETs formed over the first active area, wherein first gate electrodes of the first n-type MISFETs extend in a second direction perpendicular to the first direction and wherein second gate electrodes of the second n-type MISFETs extend in the second direction; and
a plurality of third n-type MISFETs and a plurality of fourth n-type MISFETs formed over the second active area, wherein third gate electrodes of the third n-type MISFETs extend in the second direction and wherein fourth gate electrodes of the fourth n-type MISFETs extend in the second direction,
wherein each of the memory cells includes one of the first n-type MISFETs, one of the second n-type MISFETs, one of the third n-type MISFETs, and one of the fourth n-type MISFETs,
wherein a width in the second direction of a first terminal section of the first active area is larger than a width in the second direction of the first active area where the first and second n-type MISFETs are formed, and
wherein a width in the second direction of a second terminal section of the second active area is larger than a width in the second direction of the second active area where the third and fourth n-type MISFETs are formed.
2. The semiconductor device according to claim 1 ,
wherein the width of the first terminal section of the first active area in the second direction is largest among the widths of the first active area in the second direction, and
wherein the width of the second terminal section of the second active area in the second direction is largest among the widths of the second active area in the second direction.
3. The semiconductor device according to claim 2 ,
wherein the width of the first terminal section of the first active area in the second direction is equal to or larger than 1.5 times the width of the narrowest area of the first active area in the second direction, and
wherein the width of the second terminal section of the second active area in the second direction is equal to or larger than 1.5 times the width of the narrowest area of the second active area in the second direction.
4. The semiconductor device according to claim 1 ,
wherein the first and second active areas are implanted with nitrogen.
5. The semiconductor device according to claim 1 ,
wherein the first terminal section of the first active area is bent to the second direction, and
wherein the second terminal section of the second active area is bent to the second direction.
6. The semiconductor device according to claim 5 ,
wherein the first terminal section of the first active area is in an L shape, and
wherein the second terminal section of the second active area is in an L shape.
7. The semiconductor device according to claim 1 ,
wherein a plurality of first p-type MISFETs and a plurality of second p-type MISFETs are arranged between the first active area and the second active area, and
wherein each of the memory cells further includes one of the first p-type MISFETs and one of the second p-type MISFETs.
8. The semiconductor device according to claim 7 ,
wherein a first substrate potential supply section is formed in the semiconductor substrate and is adjacent with the first terminal section in the first direction, and
wherein a second substrate potential supply section is formed in the semiconductor substrate and is adjacent with the second terminal section in the first direction.
9. The semiconductor device according to claim 1 ,
wherein a first substrate potential supply section is formed in the semiconductor substrate and is adjacent with the first terminal section in the first direction, and
wherein a second substrate potential supply section is formed in the semiconductor substrate and is adjacent with the second terminal section in the first direction.
10. The semiconductor device according to claim 1 ,
wherein the second terminal section of one memory cell is coupled with the first terminal of the other memory cell which is adjacent in the second direction.
11. The semiconductor device according to claim 10 ,
wherein a plurality of first p-type MISFETs and a plurality of second p-type MISFETs are arranged between the first active area and the second active area, and
wherein each of the memory cells further includes one of the first p-type MISFETs and one of the second p-type MISFETs.
12. The semiconductor device according to claim 11 ,
wherein a first substrate potential supply section is formed in the semiconductor substrate and is adjacent with the first terminal section in the first direction, and
wherein a second substrate potential supply section is formed in the semiconductor substrate and is adjacent with the second terminal section in the first direction.
13. The semiconductor device according to claim 10 ,
wherein a first substrate potential supply section is formed in the semiconductor substrate and is adjacent with the first terminal section in the first direction, and
wherein a second substrate potential supply section is formed in the semiconductor substrate and is adjacent with the second terminal section in the first direction.
14. A semiconductor device including a plurality of memory cells of SRAM, comprising:
a semiconductor substrate;
an element isolation region formed by filling a trench formed in the semiconductor substrate with an insulating film;
a first active region which is defined by the element isolation region, which is formed by implanting a first conductive impurity into the semiconductor substrate and which extends in a first direction so as to span two or more of said memory cells;
a second active region which is defined by the element isolation region, and which is formed by implanting the first conductive impurity into the semiconductor substrate, and which extends in the first direction so as to span two or more of said memory cells and which is isolated from the first active region by the element isolation region;
a plurality of first n-type MISFETs and a plurality of second n-type MISFETs formed over the first active region, wherein first gate electrodes of the first n-type MISFETs extend in a second direction perpendicular to the first direction and wherein second gate electrodes of the second n-type MISFETs extend in the second direction; and
a plurality of third n-type MISFETs and a plurality of fourth n-type MISFETs formed over the second active region, wherein third gate electrodes of the third n-type MISFETs extend in the second direction and wherein fourth gate electrodes of the fourth n-type MISFETs extend in the second direction,
wherein each of the memory cells includes one of the first n-type MISFETs, one of the second n-type MISFETs, one of the third n-type MISFETs, and one of the fourth n-type MISFETs,
wherein the semiconductor device further comprises first and second dummy electrodes formed in the same layer as the first, second, third, and fourth gate electrodes and extending in the second direction,
wherein the first dummy electrode overlaps with the first terminal section of the first active area on a plane, and
wherein the second dummy electrode overlaps with the second terminal section of the second active area on a plane.
15. The semiconductor device according to claim 14 ,
wherein a plurality of first p-type MISFETs and a plurality of second p-type MISFETs are arranged between the first active region and the second active region, and
wherein each of the memory cells further includes one of the first p-type MISFETs and one of the second p-type MISFETs.
16. The semiconductor device according to claim 15 ,
wherein a first substrate potential supply section is formed in the semiconductor substrate and is adjacent with the first terminal section in the first direction, and
wherein a second substrate potential supply section is formed in the semiconductor substrate and is adjacent with the second terminal section in the first direction.
17. The semiconductor device according to claim 14 ,
wherein a first substrate potential supply section is formed in the semiconductor substrate and is adjacent with the first terminal section in the first direction, and
wherein a second substrate potential supply section is formed in the semiconductor substrate and is adjacent with the second terminal section in the first direction.
18. A semiconductor device including a plurality of memory cells of SRAM, comprising:
a semiconductor substrate;
an element isolation region formed by filling a trench formed in the semiconductor substrate with an insulating film;
a first active region which is defined by the element isolation region, which is formed by implanting a first conductive impurity into the semiconductor substrate and which extends in a first direction so as to span two or more of said memory cells; and
a plurality of first n-type MISFETs and a plurality of second n-type MISFETs formed over the first active region, wherein first gate electrodes of the first n-type MISFETs extend in a second direction perpendicular to the first direction and wherein second gate electrodes of the second n-type MISFETs extend in the second direction,
wherein each of the memory cells includes one of the first n-type MISFETs and one of the second n-type MISFETs, and
wherein a width in the second direction of a first terminal section of the first active area is larger than a width in the second direction of the first active area where the first and second n-type MISFETs are formed further comprising: a second active region which is defined by the element isolation region, and which is formed by implanting the first conductive impurity into the semiconductor substrate, and which extends in the first direction so as to span two or more of said memory cells and which is isolated from the first active region by the element isolation region; and a plurality of third n-type MISFETs and a plurality of fourth n-type MISFETs formed over the second active region, wherein third gate electrodes of the third n-type MISFETs extend in the second direction and wherein fourth gate electrodes of the fourth n-type MISFETs extend in the second direction, wherein each of the memory cells further includes one of the third n-type MISFETs and one of the fourth n-type MISFETs, and wherein a width in the second direction of a second terminal section of the second active area is larger than a width in the second direction of the second active area where the third and fourth n-type MISFETs are formed.
19. The semiconductor device according to claim 18 ,
wherein a plurality of first p-type MISFETs and a plurality of second p-type MISFETs are arranged between the first active region and the second active region,
wherein each of the memory cells further includes one of the first p-type MISFETs and one of the second p-type MISFETs,
wherein a first substrate potential supply section is formed in the semiconductor substrate and is adjacent with the first terminal section in the first direction,
wherein a second substrate potential supply section is formed in the semiconductor substrate and is adjacent with the second terminal section in the first direction,
wherein a first substrate potential supply section is formed in the semiconductor substrate and is adjacent with the first terminal section in the first direction,
wherein a second substrate potential supply section is formed in the semiconductor substrate and is adjacent with the second terminal section in the first direction, and
wherein the second terminal section of one memory cell is coupled with the first terminal of the other memory cell which is adjacent in the second direction.