IP Library Granted Patent US 8,724,763
Granted Patent B2
US 8,724,763 · App. 12/262,239 · Granted May 13, 2014

Method and apparatus for frame-based buffer control in a communication system

Inventors: Christof Faller (Murray Hill, NJ); Raziel Haimi-Cohen (Springfield, NJ)
Assignee: Agere Systems LLC
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Quick Facts
Patent No.
US 8,724,763
App. No.
12/262,239
Granted
May 13, 2014
Kind
B2
Abstract

A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The transmitter predicts the number of encoded frames, F pred , in the buffer having a limited level and transmits the value, F pred , to the receiver with the frame. If the transmitter determines that the decoder buffer level is high, the frames being generated by the encoder are small and additional bits are allocated to each frame for each of the N programs. Likewise, if the transmitter determines that the decoder buffer level is becoming low, the frames being generated by the encoder are big and fewer bits are allocated to each frame for each of the N programs. The transmitted predicted buffer level, F pred , can also be employed to (i) determine when the decoder should commence decoding frames; and (ii) synchronize the transmitter and the receiver clock using feedback depending on the compared level of the decoder to the actual level to F pred .

Claims (32)

1. A method for synchronizing a receiver and a transmitter in a communication system, said method comprising the steps of:

receiving a number indicating a predicted number of encoded frames in a buffer;

comparing said number indicating a predicted number of encoded frames to an actual number of encoded frames in said buffer; and

adjusting a clock frequency based on said comparison.

2. The method of claim 1 , wherein said communication system is a digital audio broadcasting (DAB) system.

3. The method of claim 1 , wherein predicted number of encoded frames indicates a number of encoded frames in a decoder buffer.

4. The method of claim 1 , wherein said predicted number of encoded frames considers a respective data rate of an encoder and a decoder and a channel bit rate of said communication system.

5. The method of claim 1 , wherein said predicted number of encoded frames is determined by an encoder and wherein said buffer is a decoder buffer.

6. The method of claim 1 , wherein said adjusting step increases said clock frequency if said predicted number of encoded frames is lower than said actual number of encoded frames in said buffer.

7. The method of claim 1 , wherein said adjusting step decreases said clock frequency if said predicted number of encoded frames is higher than said actual number of encoded frames in said buffer.

8. A system for synchronizing a receiver and a transmitter in a communication system, comprising:

a memory that stores computer-readable code; and

a processor operatively coupled to said memory, said processor configured to implement said computer-readable code, said computer-readable code configured to:

receive a number indicating a predicted number of encoded frames in a buffer;

compare said number indicating a predicted number of encoded frames to an actual number of encoded frames in said buffer; and

adjust a clock frequency based on said comparison.

9. The system of claim 8 , wherein said communication system is a digital audio broadcasting (DAB) system.

10. The system of claim 8 , wherein predicted number of encoded frames indicates a number of encoded frames in a decoder buffer.

11. The system of claim 8 , wherein said predicted number of encoded frames considers a respective data rate of an encoder and a decoder and a channel bit rate of said communication system.

12. The system of claim 8 , wherein said predicted number of encoded frames is determined by an encoder and wherein said buffer is a decoder buffer.

13. The system of claim 8 , wherein said adjusting step increases said clock frequency if said predicted number of encoded frames is lower than said actual number of encoded frames in said buffer.

14. The system of claim 8 , wherein said adjusting step decreases said clock frequency if said predicted number of encoded frames is higher than said actual number of encoded frames in said buffer.

15. A system for synchronizing a receiver and a transmitter in a communication system, comprising:

a buffer for storing frames of encoded data;

an input port for receiving a number indicating a predicted number of encoded frames in a buffer;

means for comparing said number indicating a predicted number of encoded frames to an actual number of encoded frames in said buffer; and

means for adjusting a clock frequency based on said comparison.

16. The system of claim 15 , wherein said communication system is a digital audio broadcasting (DAB) system.

17. The system of claim 15 , wherein predicted number of encoded frames indicates a number of encoded frames in a decoder buffer.

18. The system of claim 15 , wherein said predicted number of encoded frames considers a respective data rate of an encoder and a decoder and a channel bit rate of said communication system.

19. The system of claim 15 , wherein said adjusting step increases said clock frequency if said predicted number of encoded frames is lower than said actual number of encoded frames in said buffer.

20. The system of claim 15 , wherein said adjusting step decreases said clock frequency if said predicted number of encoded frames is higher than said actual number of encoded frames in said buffer.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
CERTIFICATE OF CONVERSION Recorded Mar 5, 2014
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 032389/0086 →
Continuity (2)
Division 09895926 · Jun 29, 2001
Related Publication 20090052601A1 · Feb 26, 2009