Controllable circuit

1. A circuit comprising:

a controllable element that controls a load current in response to a control signal supplied to the controllable element; and

a control unit that provides the control signal, the control unit comprising

a first signal processing unit that receives a first carrier signal and an input signal, and provides a first output signal;

a second signal processing unit that receives a second carrier signal and the input signal, and provides a second output signal; and

a combiner unit that combines the first and the second output signals to form a signal representative of the control signal;

where the first and the second carrier signals are different frequencies.

2. The circuit of claim 1 , where the controllable element comprises a controllable switch configured to switch the load current on and off dependant on the control signal and where the combiner unit comprises a logic unit that combines the first and second output signals to form a binary signal representative of the control signal.

3. The circuit of claim 2 , where the logic unit provides one of an OR operation, an AND operation and an OR-AND operation.

4. The circuit of claim 3 , where

the logic unit further comprises a first AND gate, a first OR gate and a second OR gate, each gate having at least two inputs and an output;

the inputs of the first AND gate and the first OR gate are each coupled with the outputs of the first and the second signal processing units; and

the outputs of the first AND gate and the first OR gate are coupled with the inputs of the second OR gate, the second OR gate having an output providing the control signal.

5. The circuit of claim 4 , where

one of the first and the second carrier signals is a master carrier signal having a slope; and

the output of at least one of the first AND gate and the first OR gate provides the control signal that is a function of the slope of the master carrier signal.

6. The circuit of claim 4 , where

the logic unit further comprises a second AND gate and a third AND gate, each gate having two or more inputs and an output;

the second AND gate is supplied with a differentiated master carrier element and the output of the first AND gate;

the third AND gate is supplied with an inverted differentiated element and the output of the first OR gate; and

the second OR gate is connected to the outputs of the second and the third AND gates, the second OR gate providing the control signal.

7. The circuit of claim 6 , where the control signal further comprises alternating pulses from the first OR gate and the first AND gate.

8. The circuit of claim 7 , where

the logic unit further comprises a second AND gate, a third AND gate, and a sample element, each gate and the sample element having one or more inputs and an output;

one input of the sample element is supplied with an inverted output signal of the sample element;

the second AND gate is connected to the outputs of the sample element and the first AND gate;

the third AND gate is connected to an inverted output of the sample element and the output of the first OR gate; and

the second OR gate is connected to the outputs of the second and the third AND gates and provides the control signal.

9. The circuit of claim 2 , where each of the first and the second signal processing units further comprise comparators, each comparator having inputs and an output, the inputs supplied with the input signal and one of the carrier signals.

10. The circuit of claim 2 , where the first and the second signal processing units are adapted to generate pulse width modulated signals.

11. The circuit of claim 1 , where the first and the second carrier signals comprise one of a rectangular, a sinusoidal, and a triangular waveform.

12. The circuit of claim 11 , where the first and the second carrier signals are clock signals having a rectangular waveform.

13. The circuit of claim 1 , where the controllable element comprises a transistor.

14. The circuit of claim 1 , where the signal processing unit comprises a modulator.