IP Library Granted Patent US 8,433,553
Granted Patent B2
US 8,433,553 · App. 12/264,085 · Granted Apr 30, 2013

Method and apparatus for designing a processor

Inventors: Alexander Augusteijn (Eindhoven, NL); Jeroen Anton Johan Leijten (Hulsel, NL)
Assignee: Intel Benelux B.V.
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Quick Facts
Patent No.
US 8,433,553
App. No.
12/264,085
Granted
Apr 30, 2013
Kind
B2
Abstract

A programmed computer and method are described for generating a processor design. The method carried out by the programmed computer comprises providing an initial model for the processor, specifying a plurality of resources in terms of resource parameters and their mutual relations. Furthermore, statistics are provided indicative of the required use of the resources by a selected application. Thereafter, a reduced resource design is generated by the programmed computer by relaxing at least one resource parameter and/or limiting an amount of resources specified in the initial specification on the basis of the statistics.

Claims (27)

1. A method for generating, on a programmed computer system comprising a server station with a first programmed facility and a client station with a second, a third and a fourth programmed facility, a processor design, the method comprising the steps of:

providing an initial model for the processor to the first programmed facility, the initial model specifying a plurality of resources in terms of resource parameters and their mutual relations,

providing a selected application to the second programmed facility,

compiling, by the third programmed facility including a compiler, software used by the selected application,

the compiler, included in the third programmed facility, providing statistics indicative of resources required for use by the selected application, and relaxing at least one resource parameter and/or limiting an amount of resources specified in the initial model specification by the fourth programmed facility on the basis of the statistics.

2. The method according to claim 1 , wherein the resources comprise at least one of processing resources, storage resources and communication resources.

3. The method according to claim 1 , wherein the processor is a VLIW processor.

4. The method according to claim 1 , wherein the processor is a time-stationary processor.

5. The method according to claim 1 , wherein the processor is a data-stationary processor.

6. The method according to claim 1 , wherein the processor is a microcoded processor.

7. A design computer system including a computer readable medium including computer executable instructions for generating a processor design, the computer system comprising a server station and a client station:

the server station having a first programmed facility for receiving an initial model for the processor, the initial model specifying a plurality of resources in terms of resource parameters and their mutual relations,

the client station having a second programmed facility for receiving a selected application,

the client station having a third programmed facility for compiling software used by the selected application with a compiler,

the design computer system further comprising said third programmed facility for providing statistics indicative of resources required for use by the selected application with said compiler,

the client station having a fourth programmed facility for relaxing at least one resource parameter and/or limiting an amount of resources specified in the initial model specification on the basis of the statistics.

8. A non-transitory computer-readable medium including computer-executable instructions for causing a computer system comprising a server station and a client station to generate a processor design by performing the steps of:

causing the server station to provide an initial model for the processor, specifying a plurality of resources in terms of resource parameters and their mutual relations,

causing the server station to provide a selected application,

causing the client station to compile the selected application with a compiler,

said compiler providing statistics indicative of resources required for use by the selected application, and

causing the client station to relax at least one resource parameter and/or limiting an amount of resources specified in the initial model specification on the basis of the statistics.

9. The non-transitory computer-readable medium according to claim 8 , wherein the resources comprise at least one of processing resources, storage resources and communication resources.

10. The non-transitory computer-readable medium according to claim 8 , wherein the processor is a VLIW processor.

11. The non-transitory computer-readable medium according to claim 8 , wherein the processor is a time-stationary processor.

12. The non-transitory computer-readable medium according to claim 8 , wherein the processor is a data-stationary processor.

13. The non-transitory computer-readable medium according to claim 8 , wherein the processor is a microcoded processor.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2014
From: INTEL BENELUX B.V.
To: INTEL CORPORATION
Reel/Frame 031926/0502 →
"SILOCON HIVE B.V." SHOULD BE SPELLED "SILICON HIVE B.V" ASSIGNEE:"INTEL CORPORATION" SHOULD BE REMOVED. RECORDED ON REEL/FRAME:028883/0689 (502045456) Recorded Nov 21, 2012
From: SILICON HIVE B. V.
To: INTEL BENELUX B. V.
Reel/Frame 029405/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2012
From: SILICON HIVE B.V.
To: INTEL BENELUX B.V.
Reel/Frame 028883/0689 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2009
From: AUGUSTEIJN, ALEXANDER; LEIJTEN, JEROEN ANTON JOHAN
To: SILICON HIVE B.V.
Reel/Frame 022070/0590 →
Continuity (2)
Provisional Application 60984593 · Nov 1, 2007
Related Publication 20090281784A1 · Nov 12, 2009