Semiconductor package having insulated metal substrate and method of fabricating the same
View Patent ↗Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns.
1. A semiconductor package comprising:
a substrate comprising a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer;
semiconductor chips arranged on the conductive patterns;
solder mask patterns arranged on the conductive patterns to surround the semiconductor chips;
leads electrically connected to the conductive patterns through wires; and
a sealing member arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns.
2. The semiconductor package of claim 1 wherein the solder mask patterns are arranged to expose edges of the conductive patterns in order to increase the adhesion of the sealing member to the substrate.
3. The semiconductor package of claim 2 , wherein the sealing member comprises an epoxy resin.
4. The semiconductor package of claim 1 , wherein contact areas between the sealing member and the conductive patterns are relatively greater than a contact areas between the sealing member and the solder mask patterns.
5. The semiconductor package of claim 1 , wherein the solder mask patterns comprise an epoxy resin.
6. The semiconductor package of claim 1 , wherein the base member comprises an Al plate.
7. The semiconductor package of claim 1 , wherein the conductive patterns are formed of Cu, Au, Ag, Al, or Ni.
8. The semiconductor package of claim 7 , wherein the conductive patterns are formed of Cu, Au, Ag, Al, or Ni.
9. The semiconductor package of claim 7 , wherein the semiconductor package comprises a power module package.
10. The semiconductor package of claim 1 , wherein the semiconductor package comprises a power module package.
11. A semiconductor package comprising:
an insulation metal substrate comprising a base member formed of an Al plate, an insulating layer formed of an epoxy resin group and disposed on the base member, and conductive patterns formed on the insulating layer;
semiconductor chips arranged on the conductive patterns;
leads electrically connected to the conductive patterns through wires; and
a sealing member that comprises a transfer molded epoxy resin and is arranged on an upper surface and side surfaces of the insulation metal substrate to cover portions of the leads, the wires, and the semiconductor chips.
12. The semiconductor package of claim 11 , wherein the semiconductor chips contact conductive patterns to form corners with a lateral surface including the a conductive pattern and a vertical surface including an edge of a semiconductor chip and wherein the sealing member fills said corners and contacts the lateral and vertical surfaces forming said corners.