Multilayer semiconductor device
View Patent ↗The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips includes a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device also includes a separating element that connects the pad to a test stub line when each semiconductor chip is tested and separates the pad from the test stub line during the normal operation.
1. A semiconductor device comprising:
a first chip including a first signal line;
a second chip including a second signal line;
an internal line electrically connecting the first signal line with the second signal line; and
a printed board including a test portion for testing an electrical condition of the internal line, the test portion electrically connecting the internal line with a test external terminal when the semiconductor device is subject to a test mode in which each of the first and second signal lines is tested and the test portion electrically disconnecting the internal line from the test external terminal during a normal operation of the semiconductor device.
2. The semiconductor device according to claim 1 , wherein a part of the internal line is mounted in the printed board.
3. The semiconductor device according to claim 1 , wherein the internal line is not connected to any external terminals during the normal operation.
4. The semiconductor device according to claim 1 , wherein the first chip includes a third signal line, the second chip includes a fourth signal line, and the printed board includes first and second external terminals, the first and second external terminal connecting electrically with the third and fourth signal lines, respectively.
5. The semiconductor device according to claim 1 , wherein the test portion is an insert hole which reaches the internal line, and a conductive member is inserted into the insert hole to connect the internal line to an external measuring apparatus when the semiconductor device is subject to the test mode.
6. The semiconductor device according to claim 5 , wherein the conductive member is a connector or a probe.
7. The semiconductor device according to claim 1 , wherein the semiconductor device is a multilayer semiconductor device, and the first chip is disposed on a top surface of the second chip.