DIGITAL-ENCRYPTION HARDWARE ACCELERATOR
An electronic device for encrypting and decrypting data blocks of a message having n data blocks in accordance with the data encryption standard (DES) is provided. The electronic device has a first data processing channel having a first processing stage for performing encryption and decryption of data blocks of a predefined length, and a first input data buffer coupled to a data input and to the first processing stage, and a second data processing channel having a second processing stage for performing encryption and decryption of data blocks, a second data input buffer coupled to an output of the first processing stage and to the second processing stage. The electronic device also has a control stage (FSM) for controlling the first processing stage and the second processing stage, so as to perform an encryption or decryption step with the second processing stage on an encrypted/decrypted data block output from the first processing stage. The control stage is adapted to control the first processing stage to perform data encryption or decryption according to the data encryption standard on each block and to control the second processing stage to compute a message authentication code over the encrypted or decrypted message received from the first processing stage block-by-block.
1 . An electronic device for encrypting and decrypting data blocks of a message having n data blocks in accordance with the data encryption standard (DES), the electronic device comprising:
a first data processing channel comprising a first processing stage for performing encryption or decryption of data blocks of a predefined length, and a first input data buffer coupled to a data input and to the first processing stage; and
a second data processing channel comprising a second processing stage for performing encryption or decryption of data blocks, a second data input buffer coupled to an output of the first processing stage; and to the second processing stage;
the electronic device further comprising a control stage (FSM) for controlling the first processing stage and the second processing stage, so as to perform an encryption or decryption step with the second processing stage on an encrypted/decrypted data block output from the first processing stage, wherein the control stage is adapted to control the first processing stage to perform data encryption or decryption according to the data encryption standard on each block and to control the second processing stage to compute a message authentication code over the encrypted/decrypted message received from the first processing stage block-by-block.
2 . The electronic device according to claim 1 , further comprising a first key register for storing a first encryption or decryption key to be used by the first processing stage, and a second key register for storing a second encryption or decryption key to be used by the second processing stage.
3 . The electronic device according to claim 1 , wherein the second input data buffer has twice the size of the first data buffer.
4 . The electronic device according to claim 2 , wherein the second input data buffer has twice the size of the first data buffer.
5 . The electronic device according to claim 1 , wherein the first processing stage and the second processing stage are both adapted to perform single-DES and triple-DES operations.
6 . The electronic device according to claim 2 , wherein the first processing stage and the second processing stage are both adapted to perform single-DES and triple-DES operations.
7 . The electronic device according to claim 3 , wherein the first processing stage and the second processing stage are both adapted to perform single-DES and triple-DES operations.
8 . The electronic device according to claim 4 , wherein the first processing stage and the second processing stage are both adapted to perform single-DES and triple-DES operations.
9 . The electronic device according to claim 2 , wherein the first and the second encryption and/or decryption key has a maximum length of 128 Bit.
10 . The electronic device according to claim 3 , wherein the first and the second encryption and/or decryption key has a maximum length of 128 Bit.
11 . The electronic device according to claim 4 , wherein the first and the second encryption and/or decryption key has a maximum length of 128 Bit.
12 . The electronic device according to claim 1 , wherein the first channel is adapted to perform ECB mode and CBC mode for encryption and decryption and the second channel is adapted to perform ECB for encryption and decryption and CBC mode for encryption only.
13 . The electronic device according to claim 2 , wherein the first channel is adapted to perform ECB mode and CBC mode for encryption and decryption and the second channel is adapted to perform ECB for encryption and decryption and CBC mode for encryption only.
14 . The electronic device according to claim 3 , wherein the first channel is adapted to perform ECB mode and CBC mode for encryption and decryption and the second channel is adapted to perform ECB for encryption and decryption and CBC mode for encryption only.
15 . The electronic device according to claim 5 , wherein the first channel is adapted to perform ECB mode and CBC mode for encryption and decryption and the second channel is adapted to perform ECB for encryption and decryption and CBC mode for encryption only.
16 . The electronic device according to claim 6 , wherein the first channel is adapted to perform ECB mode and CBC mode for encryption and decryption and the second channel is adapted to perform ECB for encryption and decryption and CBC mode for encryption only.
17 . The electronic device according to claim 9 , wherein the first channel is adapted to perform ECB mode and CBC mode for encryption and decryption and the second channel is adapted to perform ECB for encryption and decryption and CBC mode for encryption only.
18 . The electronic device according to claim 1 , wherein a data block has a length of 64 Bit.
19 . A method for encrypting a message having n data blocks, the method comprising: encrypting a data block in a first processing stage in accordance with a single-DES or triple-DES operation, passing the encrypted data block to a second processing stage, and encrypting the encrypted data block in the second processing stage in accordance with a single-DES or triple-DES operation, wherein the first encrypting step performs data encryption on each block and the second encrypting step performs computation of a message authentication code over the encrypted message block-by-block.
20 . A method for decrypting a message having n encrypted data blocks and a message authentication code, the method comprising: decrypting a data block in a first processing stage in accordance with a single-DES or triple-DES operation, passing the decrypted data block to a second processing stage, decrypting the decrypted data block in the second processing stage in accordance with a single-DES or triple-DES operation, wherein the first decrypting step performs data decryption on each block and the second decrypting step retrieves the message authentication code from n blocks.