Variability-Aware Asynchronous Scheme Based on Two-Phase Protocols
A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.
1 . A circuit structure for the conversion of a synchronous circuit to an asynchronous circuit comprising:
a data circuit with at least two level-sensitive latches, each of the latches comprising at least one bit of information and each of the latches including at least one enable signal;
at least one control circuit for communicating with at least one other circuit using two signals and a two-phase handshake protocol; and
at least one enable signal between said least one control circuit to at least one said level-sensitive latch, wherein the at least one enable signal is operable to enable the level-sensitive latch.
2 . The control circuit of claim 1 further comprising:
a first C-element that generates a transition on a first control signal;
a first pulse generator that transforms every transition of the said first control signal into a pulse operable to enable at least one level-sensitive latch;
a second C-element that generates a transition on a second control signal; and
a second pulse generator that transforms every transition of the said second control signal into a pulse operable to enable at least one level-sensitive latch.
3 . The circuit structure of claim 1 wherein the at least two level-sensitive latches are organized into one or more flip-flops.
4 . The control circuit of claim 2 wherein at least one of said first C-element or said second C-element includes a reset signal input.
5 . The control circuit of claim 2 further comprising:
at least one request input signal;
at least one acknowledge input signal;
at least one request output signal; and
at least one acknowledge output signal.
6 . The circuit structure of claim 1 wherein the at least one control circuit for communicating with at least one other circuit is incorporated within a semiconductor chip package.
7 . The circuit structure of claim 1 wherein the at least one control circuit for communicating with at least one other circuit is incorporated in an electronic system.
8 . A method for synthesizing a circuit structure for the conversion of a synchronous circuit to an asynchronous circuit comprising:
outputting a data circuit with at least two level-sensitive latches, each of the latches comprising at least one bit of information and each of the latches including at least one enable signal;
outputting at least one control circuit for communicating with at least one other circuit using two signals and a two-phase handshake protocol; and
outputting at least one enable signal between said least one control circuit to at least one said level-sensitive latch, wherein the at least one enable signal is operable to enable the level-sensitive latch.
9 . The method of claim 8 further comprising:
outputting a first C-element that generates a transition on a first control signal;
outputting a first pulse generator that transforms every transition of the said first control signal into a pulse operable to enable at least one level-sensitive latch;
outputting a second C-element that generates a transition on a second control signal; and
outputting a second pulse generator that transforms every transition of the said second control signal into a pulse operable to enable at least one level-sensitive latch.
10 . The method of claim 8 wherein outputting at least one of said first C-element or said second C-element includes outputting a reset signal input.
11 . The method of claim 8 further comprising:
outputting at least one request input signal;
outputting at least one acknowledge input signal;
outputting at least one request output signal; and
outputting at least one acknowledge output signal.
12 . The method of claim 8 wherein the at least two level-sensitive latches are organized into one or more flip-flops.
13 . A computer program product embodied on a tangible computer readable medium for synthesizing a circuit structure for the conversion of a synchronous circuit to an asynchronous circuit comprising:
computer code for outputting a data circuit with at least two level-sensitive latches, each of the latches comprising at least one bit of information and each of the latches including at least one enable signal;
computer code for outputting at least one control circuit for communicating with at least one other circuit using two signals and a two-phase handshake protocol; and
computer code for outputting at least one enable signal between said least one control circuit to at least one said level-sensitive latch, wherein the at least one enable signal is operable to enable the level-sensitive latch.
14 . The computer program product of claim 13 further comprising:
computer code for outputting a first C-element that generates a transition on a first control signal;
computer code for outputting a first pulse generator that transforms every transition of the said first control signal into a pulse operable to enable at least one level-sensitive latch;
computer code for outputting a second C-element that generates a transition on a second control signal; and
computer code for outputting a second pulse generator that transforms every transition of the said second control signal into a pulse operable to enable at least one level-sensitive latch.
15 . The computer program product of claim 13 wherein computer code for outputting at least one of said first C-element or said second C-element includes computer code for outputting a reset signal input.
16 . The computer program product of claim 13 further comprising:
computer code for outputting at least one request input signal;
computer code for outputting at least one acknowledge input signal;
computer code for outputting at least one request output signal; and
computer code for outputting at least one acknowledge output signal.
17 . The computer program product of claim 13 wherein the at least two level-sensitive latches are organized into one or more flip-flops.
18 . The computer program product of claim 13 , further comprising at least one of, computer code for RTL synthesis, computer code for floorplanning, computer code for clock tree synthesis, computer code for routing, computer code for layout optimization, computer code for logic verification, computer code for physical design verification.