Variability-Aware Asynchronous Scheme for High-Performance Communication Between an Asynchronous Circuit and a Synchronous Circuit
A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.
1 . A method for interfacing a desynchronized circuit with a synchronous environment, said method comprising:
operating the desynchronized circuit while concurrently operating the synchronous circuit;
signaling a synchronization phase between said desynchronized circuit and said synchronous circuit; and
exchanging handshakes between said a desynchronized circuit and said synchronous circuit.
2 . The method of claim 1 wherein said exchanging includes at least one of, a two-phase handshake, a four-phase handshake.
3 . The method of claim 1 wherein said exchanging includes a synchronization phase and a burst phase.
4 . The method of claim 3 wherein said exchanging includes a short synchronization phase and a long burst phase.
5 . A method for synthesizing an interfacing circuit for interfacing a desynchronized circuit with an external synchronous circuit, said method comprising:
classifying the desynchronized circuit as at least one of, a two-phase desynchronized circuit, a four-phase desynchronized circuit.
outputting at least one of, a two-phase desynchronized interface, a four-phase desynchronized interface; and
outputting an asynchronous to synchronous communication interface circuit.
6 . An asynchronous to synchronous communication interface circuit for transmitting data between a desynchronized circuit and a synchronous circuit said interface circuit consisting of:
a synchronizer section free of storage for storing transmitted data; and
a burst transmission section free of storage for storing transmitted data.
7 . The circuit of claim 6 wherein said synchronizer section includes a chain of flip-flops.
8 . A computer program product embodied on a tangible computer readable medium for synthesizing an interfacing circuit for interfacing a desynchronized circuit with an external synchronous circuit, said method comprising:
computer code for classifying the desynchronized circuit as at least one of, a two-phase desynchronized circuit, a four-phase desynchronized circuit.
computer code for outputting at least one of, a two-phase desynchronized interface, a four-phase desynchronized interface; and
computer code for outputting an asynchronous to synchronous communication interface circuit.
9 . The computer program product of claim 8 , further comprising at least one of, computer code for RTL synthesis, computer code for floorplanning, computer code for clock tree synthesis, computer code for routing, computer code for layout optimization, computer code for logic verification, computer code for physical design verification.